CHV/BSW supports DeGamma color correction feature, which linearizes all the non-linear color values. This will be applied before Color Transformation.
This patch does the following: 1. Adds the core function to program DeGamma correction values for CHV/BSW platform 2. Adds DeGamma correction macros/defines
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi Kausal.Malladi@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 4 ++ drivers/gpu/drm/i915/intel_atomic.c | 2 + drivers/gpu/drm/i915/intel_color_manager.c | 110 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 5 ++ drivers/gpu/drm/i915/intel_drv.h | 2 + 5 files changed, 123 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 36672e7..58a1414 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7903,11 +7903,15 @@ enum skl_disp_power_wells { /* Color Management */ #define PIPEA_CGM_CONTROL (VLV_DISPLAY_BASE + 0x67A00) #define PIPEA_CGM_GAMMA_MIN (VLV_DISPLAY_BASE + 0x67000) +#define PIPEA_CGM_DEGAMMA_MIN (VLV_DISPLAY_BASE + 0x66000) #define CGM_OFFSET 0x2000 #define GAMMA_OFFSET 0x2000 +#define DEGAMMA_OFFSET 0x2000 #define _PIPE_CGM_CONTROL(pipe) \ (PIPEA_CGM_CONTROL + (pipe * CGM_OFFSET)) #define _PIPE_GAMMA_BASE(pipe) \ (PIPEA_CGM_GAMMA_MIN + (pipe * GAMMA_OFFSET)) +#define _PIPE_DEGAMMA_BASE(pipe) \ + (PIPEA_CGM_DEGAMMA_MIN + (pipe * DEGAMMA_OFFSET))
#endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index 21f0ac2..570af9d 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -478,6 +478,8 @@ int intel_crtc_atomic_set_property(struct drm_crtc *crtc,
if (property == config->prop_palette_after_ctm) return intel_color_manager_set_gamma(dev, &crtc->base, val); + if (property == config->prop_palette_before_ctm) + return intel_color_manager_set_degamma(dev, &crtc->base, val);
DRM_DEBUG_KMS("Unknown crtc property '%s'\n", property->name); return -EINVAL; diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index 84cc3e47..21c499f 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -27,6 +27,105 @@
#include "intel_color_manager.h"
+int chv_set_degamma(struct drm_device *dev, uint32_t blob_id, + struct drm_crtc *crtc) +{ + struct drm_palette *degamma_data; + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_property_blob *blob; + struct drm_mode_config *config = &dev->mode_config; + u32 cgm_control_reg = 0; + u32 cgm_degamma_reg = 0; + enum pipe pipe; + u16 red, green, blue; + u32 count = 0; + struct drm_r32g32b32 *correction_values = NULL; + u32 num_samples; + u32 word; + int ret = 0, length; + + blob = drm_property_lookup_blob(dev, blob_id); + if (!blob) { + DRM_ERROR("Invalid Blob ID\n"); + return -EINVAL; + } + + degamma_data = (struct drm_palette *)blob->data; + + if (degamma_data->version != CHV_DEGAMMA_DATA_STRUCT_VERSION) { + DRM_ERROR("Invalid DeGamma Data struct version\n"); + return -EINVAL; + } + + pipe = to_intel_crtc(crtc)->pipe; + num_samples = degamma_data->palette_num_samples; + length = num_samples * sizeof(struct drm_r32g32b32); + + if (num_samples == 0) { + + /* Disable DeGamma functionality on Pipe - CGM Block */ + cgm_control_reg = I915_READ(_PIPE_CGM_CONTROL(pipe)); + cgm_control_reg &= ~CGM_DEGAMMA_EN; + I915_WRITE(_PIPE_CGM_CONTROL(pipe), cgm_control_reg); + + DRM_DEBUG_DRIVER("DeGamma disabled on Pipe %c\n", + pipe_name(pipe)); + ret = 0; + } else if (num_samples == CHV_DEGAMMA_MAX_VALS) { + cgm_degamma_reg = _PIPE_DEGAMMA_BASE(pipe); + + count = 0; + correction_values = + (struct drm_r32g32b32 *)°amma_data->palette_lut; + while (count < CHV_DEGAMMA_MAX_VALS) { + blue = correction_values[count].b32; + green = correction_values[count].g32; + red = correction_values[count].r32; + + blue = blue >> CHV_DEGAMMA_MSB_SHIFT; + green = green >> CHV_DEGAMMA_MSB_SHIFT; + red = red >> CHV_DEGAMMA_MSB_SHIFT; + + /* Green (29:16) and Blue (13:0) in DWORD1 */ + word = (green << CHV_DEGAMMA_GREEN_SHIFT) | blue; + I915_WRITE(cgm_degamma_reg, word); + + cgm_degamma_reg += 4; + + /* Red (13:0) to be written to DWORD2 */ + word = red; + I915_WRITE(cgm_degamma_reg, word); + + cgm_degamma_reg += 4; + count++; + } + + DRM_DEBUG_DRIVER("DeGamma LUT loaded for Pipe %c\n", + pipe_name(pipe)); + + /* Enable DeGamma on Pipe */ + I915_WRITE(_PIPE_CGM_CONTROL(pipe), + I915_READ(_PIPE_CGM_CONTROL(pipe)) | CGM_DEGAMMA_EN); + + DRM_DEBUG_DRIVER("DeGamma correction enabled on Pipe %c\n", + pipe_name(pipe)); + ret = 0; + } else { + DRM_ERROR("Invalid number of samples for DeGamma LUT\n"); + return -EINVAL; + } + + ret = drm_property_replace_global_blob(dev, &blob, length, + (void *) degamma_data, &crtc->base, + config->prop_palette_before_ctm); + + if (ret) { + DRM_ERROR("Error updating DeGamma blob\n"); + return -EFAULT; + } + + return ret; +} int chv_set_gamma(struct drm_device *dev, uint32_t blob_id, struct drm_crtc *crtc) { @@ -181,6 +280,17 @@ int intel_color_manager_set_gamma(struct drm_device *dev, return -EINVAL; }
+int intel_color_manager_set_degamma(struct drm_device *dev, + struct drm_mode_object *obj, uint32_t blob_id) +{ + struct drm_crtc *crtc = obj_to_crtc(obj); + + if (IS_CHERRYVIEW(dev)) + return chv_set_degamma(dev, blob_id, crtc); + + return -EINVAL; +} + int get_chv_pipe_capabilities(struct drm_device *dev, struct drm_color_caps *color_caps, struct drm_crtc *crtc) { diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index d83567a..64468c1 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -32,6 +32,7 @@ #define CHV_CTM_STRUCT_VERSION 1 #define CHV_PLATFORM_STRUCT_VERSION 1 #define CHV_GAMMA_DATA_STRUCT_VERSION 1 +#define CHV_DEGAMMA_DATA_STRUCT_VERSION 1
#define CHV_MAX_PALETTE_CAPS_BEFORE_CTM 1 #define CHV_MAX_PALETTE_CAPS_AFTER_CTM 2 @@ -51,6 +52,9 @@ #define CHV_10BIT_GAMMA_MSB_SHIFT 6 #define CHV_GAMMA_SHIFT_GREEN 16
+#define CHV_DEGAMMA_MSB_SHIFT 2 +#define CHV_DEGAMMA_GREEN_SHIFT 16 + #define CHV_CSC_COEFF_MAX_PRECISION 12 #define CHV_CSC_COEFF_MAX_INT 7 #define CHV_CSC_COEFF_MIN_INT -7 @@ -58,3 +62,4 @@ /* CHV CGM Block */ /* Bit 2 to be enabled in CGM block for CHV */ #define CGM_GAMMA_EN 4 +#define CGM_DEGAMMA_EN 1 diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index a7aaadf..f47d9d6 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1455,5 +1455,7 @@ void intel_color_manager_attach(struct drm_device *dev, struct drm_mode_object *mode_obj); int intel_color_manager_set_gamma(struct drm_device *dev, struct drm_mode_object *obj, uint32_t blob_id); +int intel_color_manager_set_degamma(struct drm_device *dev, + struct drm_mode_object *obj, uint32_t blob_id);
#endif /* __INTEL_DRV_H__ */