The GOP sometimes initializes the DSI pclk at a (slightly) different freq then the pclk which we pick. intel_pipe_config_compare() allows for this by doing a fuzzy compare on the port_clock.
But the pclk difference not only results in the port_clock and base.adjusted_mode.crtc_clock clocks being a bit different, but also in us picking different dsi_pll register values matching the different pclk.
This commit makes us only do the dsi_pll register compare when the adjust parameter is false, so only from verify_crtc_state(), so that we correctly do a fast modeset at boot avoiding the screen going black for about 1 sec.
Signed-off-by: Hans de Goede hdegoede@redhat.com --- drivers/gpu/drm/i915/intel_display.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b219d5858160..82fa85df0fba 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11759,8 +11759,10 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv, PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
- PIPE_CONF_CHECK_X(dsi_pll.ctrl); - PIPE_CONF_CHECK_X(dsi_pll.div); + if (!adjust) { + PIPE_CONF_CHECK_X(dsi_pll.ctrl); + PIPE_CONF_CHECK_X(dsi_pll.div); + }
if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) PIPE_CONF_CHECK_I(pipe_bpp);