On Fri, Feb 15, 2013 at 1:51 PM, Chris Wilson chris@chris-wilson.co.uk wrote:
On Fri, Feb 15, 2013 at 12:18:49AM +0000, Chris Wilson wrote:
On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9. Since we do all calculations based on them being register values (which are subtracted by 2) we need to specify them accordingly.
One thing I've just noticed is that intel_limits_i9xx_sdvo is reused by g4x, so I'll double check that in the morning unless someone beats me to it.
Okay, so gen4 share the same values for sdvo as gen3, so we are okay in fixing those up. However, the same offset-by-2 exists for the g4x values of m1,m2. And one begins to suspect all the m values. -Chris
Seems to be all M values. As we discussed on IRC this is confusing and it might be worth treating all values as according to specification and fix them up at register read/write time. Makes it easier to read, but then again, the specs play a trick on us by assuming that m1 and m2 are what we read from the regs when calculating M.
-Patrik