From: Leo Liu leo.liu@amd.com
Firmware required BO size changes in terms of ASIC family
Signed-off-by: Leo Liu leo.liu@amd.com Reviewed-by: Alex Deucher alexander.deucher@amd.com Reviewed-by: Christian König christian.koenig@amd.com --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 -- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 5 +---- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 2 +- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 13 +++++++++---- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 13 +++++++++---- 5 files changed, 20 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index ebff89e..52d6845 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1664,8 +1664,6 @@ struct amdgpu_uvd { * VCE */ #define AMDGPU_MAX_VCE_HANDLES 16 -#define AMDGPU_VCE_STACK_SIZE (1024*1024) -#define AMDGPU_VCE_HEAP_SIZE (4*1024*1024) #define AMDGPU_VCE_FIRMWARE_OFFSET 256
struct amdgpu_vce { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 803ee60..62018b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -68,9 +68,8 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work); * * First step to get VCE online, allocate memory and load the firmware */ -int amdgpu_vce_sw_init(struct amdgpu_device *adev) +int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) { - unsigned long size; const char *fw_name; const struct common_firmware_header *hdr; unsigned ucode_version, version_major, version_minor, binary_id; @@ -136,8 +135,6 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev)
/* allocate firmware, stack and heap BO */
- size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes)) + - AMDGPU_VCE_STACK_SIZE + AMDGPU_VCE_HEAP_SIZE; r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->vce.vcpu_bo); if (r) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h index b9411e4..4294854 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h @@ -24,7 +24,7 @@ #ifndef __AMDGPU_VCE_H__ #define __AMDGPU_VCE_H__
-int amdgpu_vce_sw_init(struct amdgpu_device *adev); +int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size); int amdgpu_vce_sw_fini(struct amdgpu_device *adev); int amdgpu_vce_suspend(struct amdgpu_device *adev); int amdgpu_vce_resume(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index b47c16d..f200df3 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -37,6 +37,10 @@ #include "oss/oss_2_0_d.h" #include "oss/oss_2_0_sh_mask.h"
+#define VCE_V2_0_FW_SIZE (256 * 1024) +#define VCE_V2_0_STACK_SIZE (64 * 1024) +#define VCE_V2_0_DATA_SIZE (23552 * AMDGPU_MAX_VCE_HANDLES) + static void vce_v2_0_mc_resume(struct amdgpu_device *adev); static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev); static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev); @@ -183,7 +187,8 @@ static int vce_v2_0_sw_init(struct amdgpu_device *adev) if (r) return r;
- r = amdgpu_vce_sw_init(adev); + r = amdgpu_vce_sw_init(adev, VCE_V2_0_FW_SIZE + + VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE); if (r) return r;
@@ -415,17 +420,17 @@ static void vce_v2_0_mc_resume(struct amdgpu_device *adev) WREG32(mmVCE_LMI_VM_CTRL, 0);
addr += AMDGPU_VCE_FIRMWARE_OFFSET; - size = AMDGPU_GPU_PAGE_ALIGN(adev->vce.fw->size); + size = VCE_V2_0_FW_SIZE; WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
addr += size; - size = AMDGPU_VCE_STACK_SIZE; + size = VCE_V2_0_STACK_SIZE; WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
addr += size; - size = AMDGPU_VCE_HEAP_SIZE; + size = VCE_V2_0_DATA_SIZE; WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 384c45e..ee29436f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -35,6 +35,10 @@ #include "oss/oss_2_0_d.h" #include "oss/oss_2_0_sh_mask.h"
+#define VCE_V3_0_FW_SIZE (384 * 1024) +#define VCE_V3_0_STACK_SIZE (64 * 1024) +#define VCE_V3_0_DATA_SIZE ((16 * 1024 * AMDGPU_MAX_VCE_HANDLES) + (52 * 1024)) + static void vce_v3_0_mc_resume(struct amdgpu_device *adev); static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev); static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev); @@ -181,7 +185,8 @@ static int vce_v3_0_sw_init(struct amdgpu_device *adev) if (r) return r;
- r = amdgpu_vce_sw_init(adev); + r = amdgpu_vce_sw_init(adev, VCE_V3_0_FW_SIZE + + (VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE) * 2); if (r) return r;
@@ -304,17 +309,17 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev)
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); offset = AMDGPU_VCE_FIRMWARE_OFFSET; - size = AMDGPU_GPU_PAGE_ALIGN(adev->vce.fw->size); + size = VCE_V3_0_FW_SIZE; WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
offset += size; - size = AMDGPU_VCE_STACK_SIZE; + size = VCE_V3_0_STACK_SIZE; WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
offset += size; - size = AMDGPU_VCE_HEAP_SIZE; + size = VCE_V3_0_DATA_SIZE; WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE2, size);