On Wed, Aug 18, 2021 at 09:10:36PM +0300, Jani Nikula wrote:
The bw code equals link_rate / 0.27 Gbps only for 8b/10b link rates. Handle DP 2.0 UHBR rates as special cases, though this is not pretty.
Ugh. So if I'm reading the spec right the behaviour of this register now changes dynamically depending on the state of some other bit in another register?
Cc: dri-devel@lists.freedesktop.org Signed-off-by: Jani Nikula jani.nikula@intel.com
drivers/gpu/drm/drm_dp_helper.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 6d0f2c447f3b..9b2a2961fca8 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -207,15 +207,33 @@ EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
u8 drm_dp_link_rate_to_bw_code(int link_rate) {
- /* Spec says link_bw = link_rate / 0.27Gbps */
- return link_rate / 27000;
- switch (link_rate) {
- case 1000000:
return DP_LINK_BW_10;- case 1350000:
return DP_LINK_BW_13_5;- case 2000000:
return DP_LINK_BW_20;- default:
/* Spec says link_bw = link_rate / 0.27Gbps */return link_rate / 27000;- }
} EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
int drm_dp_bw_code_to_link_rate(u8 link_bw) {
- /* Spec says link_rate = link_bw * 0.27Gbps */
- return link_bw * 27000;
- switch (link_bw) {
- case DP_LINK_BW_10:
return 1000000;- case DP_LINK_BW_13_5:
return 1350000;- case DP_LINK_BW_20:
return 2000000;- default:
/* Spec says link_rate = link_bw * 0.27Gbps */return link_bw * 27000;- }
} EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
-- 2.20.1