Changing the 400 μs to 800 μs and 400 μs did not change anything.

diff --git a/drivers/gpu/drm/radeon/atombios_dp.c
b/drivers/gpu/drm/radeon/atombios_dp.c
index 676ddf8..3e533bb 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -204,7 +204,7 @@ static int radeon_dp_aux_native_read(struct
radeon_connector *radeon_connector,
                if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
                        return ret;
                else if ((ack & AUX_NATIVE_REPLY_MASK) ==
AUX_NATIVE_REPLY_DEFER)
-                       udelay(800);
+                       udelay(200);
                else if (ret == 0)
                        return -EPROTO;
                else
@@ -293,7 +293,7 @@ int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int
mode,
                        return -EREMOTEIO;
                case AUX_NATIVE_REPLY_DEFER:
                        DRM_DEBUG_KMS("aux_ch native defer\n");
-                       udelay(800);
+                       udelay(200);
                        continue;
                default:
                        DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
@@ -310,7 +310,7 @@ int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int
mode,
                        return -EREMOTEIO;
                case AUX_I2C_REPLY_DEFER:
                        DRM_DEBUG_KMS("aux_i2c defer\n");
-                       udelay(800);
+                       udelay(200);
                        break;
                default:
                        DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
@@ -716,7 +716,7 @@ static int radeon_dp_link_train_init(struct
radeon_dp_link_train_info *dp_info)

 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info
*dp_info)
 {
-       udelay(800);
+       udelay(200);

        /* disable the training pattern on the sink */
        radeon_write_dpcd_reg(dp_info->radeon_connector,
@@ -744,7 +744,7 @@ static int radeon_dp_link_train_cr(struct
radeon_dp_link_train_info *dp_info)
        memset(dp_info->train_set, 0, 4);
        radeon_dp_update_vs_emph(dp_info);

-       udelay(800);
+       udelay(200);

        /* clock recovery loop */
        clock_recovery = false;