I'm back.

I only tested texture and uniform buffers, not SSBOs.

Results:
* Setting UBOs to 4 byte alignments didn't seem to matter in any way.
Performance didn't seem to be affected either. Nonetheless given that AMD
always sets it to 256; this is what I'd recommend (i.e. there could be
undocumented hw errors for edge cases?)

* Setting TBOs to non-16 byte alignments breaks in a specific pattern (i.e. 4
byte alignments produce certain glitches, 8 byte alignments produce a different
set of glitches, 12 byte alignments a different set, etc). Setting TBOs to 16
byte alignments fixes everything. I benchmarked 256-byte alignments vs 16-byte
alignments-non-256-byte and couldn't see any performance difference (the sample
kept around 46.50-47.00ms all the time).