1. Add pseudo-ovl definition file for mt8195 display. 2. Add mediatek,pseudo-ovl.yaml to decribe pseudo-ovl module in details.
Signed-off-by: Nancy.Lin nancy.lin@mediatek.com --- .../display/mediatek/mediatek,disp.yaml | 5 + .../display/mediatek/mediatek,pseudo-ovl.yaml | 105 ++++++++++++++++++ 2 files changed, 110 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml index aac1796e3f6b..bb6d28572b48 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml @@ -230,6 +230,11 @@ properties: - items: - const: mediatek,mt8173-disp-od
+ # PSEUDO-OVL: see Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml + # for details. + - items: + - const: mediatek,mt8195-disp-pseudo-ovl + reg: description: Physical base address and length of the function block register space.
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml new file mode 100644 index 000000000000..9059d96ce70e --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,pseudo-ovl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: mediatek pseudo ovl Device Tree Bindings + +maintainers: + - CK Hu ck.hu@mediatek.com + - Nancy.Lin nancy.lin@mediatek.com + +description: | + The Mediatek pseudo ovl function block is composed of eight RDMA and + four MERGE devices. It's encapsulated as an overlay device, which supports + 4 layers. + +properties: + compatible: + oneOf: + # pseudo ovl controller + - items: + - const: mediatek,mt8195-disp-pseudo-ovl + # RDMA: read DMA + - items: + - const: mediatek,mt8195-vdo1-rdma + # MERGE: merge streams from two RDMA sources + - items: + - const: mediatek,mt8195-vdo1-merge + reg: + maxItems: 1 + interrupts: + maxItems: 1 + iommus: + description: The compatible property is DMA function blocks. + Should point to the respective IOMMU block with master port as argument, + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for + details. + maxItems: 1 + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + power-domains: + maxItems: 1 + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: The register of display function block to be set by gce. + There are 4 arguments in this property, gce node, subsys id, offset and + register size. The subsys id is defined in the gce header of each chips + include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of + display function block. + +allOf: + - if: + properties: + compatible: + contains: + const: + - mediatek,mt8195-vdo1-merge + + then: + properties: + clocks: + items: + - description: merge clock + - description: merge async clock + clock-names: + items: + - const: merge + - const: merge_async + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + + vdo1_rdma@1c104000 { + compatible = "mediatek,mt8195-vdo1-rdma", + "mediatek,mt8195-disp-pseudo-ovl"; + reg = <0 0x1c104000 0 0x1000>; + interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>; + }; + + disp_vpp_merge@1c10c000 { + compatible = "mediatek,mt8195-vdo1-merge"; + reg = <0 0x1c10c000 0 0x1000>; + interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>; + }; + +...