Am 30.07.2012 16:56, schrieb Jerome Glisse:
On Sun, Jul 29, 2012 at 1:04 PM, Marek Olšák maraeo@gmail.com wrote:
If we don't need stencil, don't allocate it. If we need only stencil (like PIPE_FORMAT_S8_UINT), don't allocate depth.
v2: actually do it correctly
Big NAK
We need to allocate stencil and depth no matter what. Otherwise it will lockup. You can take a look by poisonning the surface and see that when stencil is disabled or depth is disabled the hw still write to it.
That seems weird - bandwidth is a precious resource. Is that because of some misconfiguration elsewhere? Or hiz buffers or the like?
Roland
Cheers, Jerome
radeon/radeon_surface.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 5800c33..874a092 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -604,7 +604,11 @@ static int eg_surface_init_1d(struct radeon_surface_manager *surf_man, } }
- if (surf->flags & RADEON_SURF_SBUFFER) {
- /* The depth and stencil buffers are in separate resources on evergreen.
* We allocate them in one buffer next to each other to simplify* communication between the DDX and the Mesa driver. */- if ((surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) ==
(RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment); surf->bo_size = surf->stencil_offset + surf->bo_size / 4;@@ -656,7 +660,8 @@ static int eg_surface_init_2d(struct radeon_surface_manager *surf_man, } }
- if (surf->flags & RADEON_SURF_SBUFFER) {
- if ((surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) ==
(RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment); surf->bo_size = surf->stencil_offset + surf->bo_size / 4;@@ -752,14 +757,7 @@ static int eg_surface_init(struct radeon_surface_manager *surf_man, /* tiling mode */ mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
- /* for some reason eg need to have room for stencil right after depth */
- if (surf->flags & RADEON_SURF_ZBUFFER) {
surf->flags |= RADEON_SURF_SBUFFER;- }
- if (surf->flags & RADEON_SURF_SBUFFER) {
surf->flags |= RADEON_SURF_ZBUFFER;- }
- if (surf->flags & RADEON_SURF_ZBUFFER) {
- if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { /* zbuffer only support 1D or 2D tiled surface */ switch (mode) { case RADEON_SURF_MODE_1D:
@@ -828,11 +826,6 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man, /* tiling mode */ mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
- /* for some reason eg need to have room for stencil right after depth */
- if (surf->flags & RADEON_SURF_ZBUFFER) {
surf->flags |= RADEON_SURF_SBUFFER;- }
- /* set some default value to avoid sanity check choking on them */ surf->tile_split = 1024; surf->bankw = 1;
-- 1.7.9.5
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