On 10/4/2021 15:06, Matthew Brost wrote:
Display the workqueue status in debugfs for GuC contexts that are in parent-child relationship.
v2: (John Harrison)
- Output number children in debugfs
Signed-off-by: Matthew Brost matthew.brost@intel.com
Reviewed-by: John Harrison John.C.Harrison@Intel.com
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 53 ++++++++++++++----- 1 file changed, 39 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index d661a69ef4f7..f69e984683aa 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -3704,6 +3704,26 @@ static inline void guc_log_context_priority(struct drm_printer *p, drm_printf(p, "\n"); }
+static inline void guc_log_context(struct drm_printer *p,
struct intel_context *ce)+{
- drm_printf(p, "GuC lrc descriptor %u:\n", ce->guc_id.id);
- drm_printf(p, "\tHW Context Desc: 0x%08x\n", ce->lrc.lrca);
- drm_printf(p, "\t\tLRC Head: Internal %u, Memory %u\n",
ce->ring->head,ce->lrc_reg_state[CTX_RING_HEAD]);- drm_printf(p, "\t\tLRC Tail: Internal %u, Memory %u\n",
ce->ring->tail,ce->lrc_reg_state[CTX_RING_TAIL]);- drm_printf(p, "\t\tContext Pin Count: %u\n",
atomic_read(&ce->pin_count));- drm_printf(p, "\t\tGuC ID Ref Count: %u\n",
atomic_read(&ce->guc_id.ref));- drm_printf(p, "\t\tSchedule State: 0x%x\n\n",
ce->guc_state.sched_state);+}
- void intel_guc_submission_print_context_info(struct intel_guc *guc, struct drm_printer *p) {
@@ -3713,22 +3733,27 @@ void intel_guc_submission_print_context_info(struct intel_guc *guc,
xa_lock_irqsave(&guc->context_lookup, flags); xa_for_each(&guc->context_lookup, index, ce) {
drm_printf(p, "GuC lrc descriptor %u:\n", ce->guc_id.id);drm_printf(p, "\tHW Context Desc: 0x%08x\n", ce->lrc.lrca);drm_printf(p, "\t\tLRC Head: Internal %u, Memory %u\n",ce->ring->head,ce->lrc_reg_state[CTX_RING_HEAD]);drm_printf(p, "\t\tLRC Tail: Internal %u, Memory %u\n",ce->ring->tail,ce->lrc_reg_state[CTX_RING_TAIL]);drm_printf(p, "\t\tContext Pin Count: %u\n",atomic_read(&ce->pin_count));drm_printf(p, "\t\tGuC ID Ref Count: %u\n",atomic_read(&ce->guc_id.ref));drm_printf(p, "\t\tSchedule State: 0x%x\n\n",ce->guc_state.sched_state);
GEM_BUG_ON(intel_context_is_child(ce));guc_log_context(p, ce);guc_log_context_priority(p, ce);
if (intel_context_is_parent(ce)) {struct guc_process_desc *desc = __get_process_desc(ce);struct intel_context *child;drm_printf(p, "\t\tNumber children: %u\n",ce->parallel.number_children);drm_printf(p, "\t\tWQI Head: %u\n",READ_ONCE(desc->head));drm_printf(p, "\t\tWQI Tail: %u\n",READ_ONCE(desc->tail));drm_printf(p, "\t\tWQI Status: %u\n\n",READ_ONCE(desc->wq_status));for_each_child(ce, child)guc_log_context(p, child);}} xa_unlock_irqrestore(&guc->context_lookup, flags); }