On 2022-02-17 at 21:39:16 -0800, Lucas De Marchi wrote:
On Tue, Feb 01, 2022 at 04:11:22PM +0530, Ramalingam C wrote:
Details of the 64k pagesize support added as part of DG2 enabling and its implicit impact on the uAPI.
v2: improvised the Flat-CCS documentation [Danvet & CQ] v3: made only for 64k pagesize support
Signed-off-by: Ramalingam C ramalingam.c@intel.com cc: Daniel Vetter daniel.vetter@ffwll.ch cc: Matthew Auld matthew.auld@intel.com cc: Simon Ser contact@emersion.fr cc: Pekka Paalanen ppaalanen@gmail.com Cc: Jordan Justen jordan.l.justen@intel.com Cc: Kenneth Graunke kenneth@whitecape.org Cc: mesa-dev@lists.freedesktop.org Cc: Tony Ye tony.ye@intel.com Cc: Slawomir Milczarek slawomir.milczarek@intel.com
Documentation/gpu/rfc/i915_dg2.rst | 25 +++++++++++++++++++++++++ Documentation/gpu/rfc/index.rst | 3 +++ 2 files changed, 28 insertions(+) create mode 100644 Documentation/gpu/rfc/i915_dg2.rst
diff --git a/Documentation/gpu/rfc/i915_dg2.rst b/Documentation/gpu/rfc/i915_dg2.rst new file mode 100644 index 000000000000..f4eb5a219897 --- /dev/null +++ b/Documentation/gpu/rfc/i915_dg2.rst @@ -0,0 +1,25 @@ +==================== +I915 DG2 RFC Section +====================
+Upstream plan +============= +Plan to upstream the DG2 enabling is:
+* Merge basic HW enabling for DG2 (Still without pciid) +* Merge the 64k support for lmem +* Merge the flat CCS enabling patches +* Add the pciid for DG2 and enable the DG2 in CI
does this make sense after the fact? Earlier version of this patch Daniel Vetter asked this to be moved to the be the first patch. I see you added it in the cover letter, but keeping this in gpu/rfc/i915_dg2.rst doesn't make much sense IMO. Maybe just drop this patch?
Yes. I couldn't move this to the start of the series as the kdoc referenced here are from later patches of the series.
But now considering we have the Kdoc for uapi at the respective patches itself we could drop this patch.
Daniel, Hope you agree on that?
Ram.
Lucas De Marchi
+64K page support for lmem +========================= +On DG2 hw, local-memory supports minimum GTT page size of 64k only. 4k is not +supported anymore.
+DG2 hw doesn't support the 64k (lmem) and 4k (smem) pages in the same ppgtt +Page table. Refer the struct drm_i915_gem_create_ext for the implication of +handling the 64k page size.
+.. kernel-doc:: include/uapi/drm/i915_drm.h
:functions: drm_i915_gem_create_extdiff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.rst index 91e93a705230..afb320ed4028 100644 --- a/Documentation/gpu/rfc/index.rst +++ b/Documentation/gpu/rfc/index.rst @@ -20,6 +20,9 @@ host such documentation:
i915_gem_lmem.rst+.. toctree::
- i915_dg2.rst
.. toctree::
i915_scheduler.rst-- 2.20.1