Re: [PATCH v2 04/11] drm/msm/disp/dpu1: Add DSC support in RM

On 07/10/2021 10:08, Vinod Koul wrote:

This add the bits in RM to enable the DSC blocks

Signed-off-by: Vinod Koul vkoul@kernel.org

Changes since v1:

• Add _dpu_rm_reserve_dsc() function which checks if DSC is enabled
• Fix to use dsc_blks

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 61 +++++++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 + 3 files changed, 63 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index 323a6bce9e64..da646817585d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -159,6 +159,7 @@ struct dpu_global_state { uint32_t ctl_to_enc_id[CTL_MAX - CTL_0]; uint32_t intf_to_enc_id[INTF_MAX - INTF_0]; uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0];

• uint32_t dsc_to_enc_id[DSC_MAX - DSC_0]; };

  struct dpu_global_state

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index f9c83d6e427a..95bdabc16280 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -11,6 +11,7 @@ #include "dpu_hw_intf.h" #include "dpu_hw_dspp.h" #include "dpu_hw_merge3d.h" +#include "dpu_hw_dsc.h" #include "dpu_encoder.h" #include "dpu_trace.h"

@@ -75,6 +76,14 @@ int dpu_rm_destroy(struct dpu_rm *rm) dpu_hw_intf_destroy(hw); } }

• for (i = 0; i < ARRAY_SIZE(rm->dsc_blks); i++) {

• struct dpu_hw_dsc *hw;
  

• if (rm->dsc_blks[i]) {
  

• 	hw = to_dpu_hw_dsc(rm->dsc_blks[i]);
  

• 	dpu_hw_dsc_destroy(hw);
  

• }
  

• }

  return 0; }

@@ -221,6 +230,19 @@ int dpu_rm_init(struct dpu_rm *rm, rm->dspp_blks[dspp->id - DSPP_0] = &hw->base; }

• for (i = 0; i < cat->dsc_count; i++) {

• struct dpu_hw_dsc *hw;
  

• const struct dpu_dsc_cfg *dsc = &cat->dsc[i];
  

• hw = dpu_hw_dsc_init(dsc->id, mmio, cat);
  

• if (IS_ERR_OR_NULL(hw)) {
  

• 	rc = PTR_ERR(hw);
  

• 	DPU_ERROR("failed dsc object creation: err %d\n", rc);
  

• 	goto fail;
  

• }
  

• rm->dsc_blks[dsc->id - DSC_0] = &hw->base;
  

• }

• return 0;

  fail:

@@ -476,6 +498,7 @@ static int _dpu_rm_reserve_intf( }

global_state->intf_to_enc_id[idx] = enc_id;

• return 0; }

@@ -500,6 +523,33 @@ static int _dpu_rm_reserve_intf_related_hw( return ret; }

+static int _dpu_rm_reserve_dsc(struct dpu_rm *rm,

• 	       struct dpu_global_state *global_state,
  

• 	       struct drm_encoder *enc)
  

+{

• struct msm_drm_private *priv;
• priv = enc->dev->dev_private;
• if (!priv)

• return -EIO;
  

• /* check if DSC is supported */
• if (!priv->dsc)

• return 0;
  

• /* check if DSC 0 & 1 and allocated or not */
• if (global_state->dsc_to_enc_id[0] || global_state->dsc_to_enc_id[1]) {

• DPU_ERROR("DSC 0|1 is already allocated\n");
  

• return -EIO;
  

• }
• global_state->dsc_to_enc_id[0] = enc->base.id;
• global_state->dsc_to_enc_id[1] = enc->base.id;

Still hardcoding DSC_0 and DSC_1.

Could you please add num_dsc to the topology and allocate the requested amount of DSC blocks? Otherwise this would break for the DSI + DP case.

• return 0;

+}

• static int _dpu_rm_make_reservation( struct dpu_rm *rm, struct dpu_global_state *global_state,

@@ -526,6 +576,10 @@ static int _dpu_rm_make_reservation( if (ret) return ret;

• ret = _dpu_rm_reserve_dsc(rm, global_state, enc);
• if (ret)

• return ret;
  

• return ret; }

@@ -567,6 +621,8 @@ void dpu_rm_release(struct dpu_global_state *global_state, ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id); _dpu_rm_clear_mapping(global_state->intf_to_enc_id, ARRAY_SIZE(global_state->intf_to_enc_id), enc->base.id);

• _dpu_rm_clear_mapping(global_state->dsc_to_enc_id,

• ARRAY_SIZE(global_state->dsc_to_enc_id), enc->base.id);
  

  }

  int dpu_rm_reserve(

@@ -640,6 +696,11 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, hw_to_enc_id = global_state->dspp_to_enc_id; max_blks = ARRAY_SIZE(rm->dspp_blks); break;

• case DPU_HW_BLK_DSC:

• hw_blks = rm->dsc_blks;
  

• hw_to_enc_id = global_state->dsc_to_enc_id;
  

• max_blks = ARRAY_SIZE(rm->dsc_blks);
  

• break;
  

  default: DPU_ERROR("blk type %d not managed by rm\n", type); return 0;

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index 1f12c8d5b8aa..278d2a510b80 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -30,6 +30,7 @@ struct dpu_rm { struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0]; struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0]; struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];

• struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];

  uint32_t lm_max_width; };