The field is encoded: 0 = 4 banks 1 = 8 banks 2 = 16 banks
Signed-off-by: Alex Deucher alexdeucher@gmail.com --- drivers/gpu/drm/radeon/evergreen.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 3c304f3..375fed7 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -2014,9 +2014,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev) break; } rdev->config.evergreen.tiling_npipes = rdev->config.evergreen.max_tile_pipes; - /* num banks is 8 on all fusion asics */ + /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */ if (rdev->flags & RADEON_IS_IGP) - rdev->config.evergreen.tiling_nbanks = 8; + rdev->config.evergreen.tiling_nbanks = 1; else rdev->config.evergreen.tiling_nbanks = ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);