CEA actually specifies an interlaced mode with even vtotal and supplies a diagram showing how this is supposed to work.
Note that interlaced modes with an even vtotal seem to be a fairly recent invention. All modelines lore I could dig up with googling says that vtotal for interlaced modes _needs_ to be odd. But the even modelines in CEA are not a spec-bug, there's a figure in CEA-861-E called "Figure 5 Special Interlaced Video Format Timing (Even Vtotal)" that explains how it's supposed to work. Furthermore intel Bspec explicitly mentions that both odd and even interlaced vtotal are supported (VTOTAL register in the south display engine of PCH split chips).
Cc: Adam Jackson ajax@redhat.com Signed-Off-by: Daniel Vetter daniel.vetter@ffwll.ch --- drivers/gpu/drm/drm_modes.c | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c index fb8e46b..7ff13bc 100644 --- a/drivers/gpu/drm/drm_modes.c +++ b/drivers/gpu/drm/drm_modes.c @@ -686,8 +686,6 @@ void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags) p->crtc_vsync_end /= 2; p->crtc_vtotal /= 2; } - - p->crtc_vtotal |= 1; }
if (p->flags & DRM_MODE_FLAG_DBLSCAN) {