26 Apr
2017
26 Apr
'17
2:30 p.m.
On Wed, Apr 26, 2017 at 11:00:09AM +0900, Michel Dänzer wrote:
On 25/04/17 06:52 PM, Ville Syrjälä wrote:
On Tue, Apr 25, 2017 at 12:18:52PM +0900, Michel Dänzer wrote:
On 24/04/17 03:25 PM, Gerd Hoffmann wrote:
+#ifdef __BIG_ENDIAN
- switch (bpp) {
- case 8:
fmt = DRM_FORMAT_C8;break;- case 24:
fmt = DRM_FORMAT_BGR888;break;BTW, endianness as a concept cannot apply to 8 or 24 bpp formats.
To 8bpp no, but it can easily apply to 24bpp.
Any byte swapping rips apart the bytes of a 24bpp pixel, so those formats only make sense as straight array formats.
In my book little endian just means "lsb is stored in the lowest memory address". The fact that your CPU/GPU can't do 3 byte swaps is not relevant for that definition IMO.
--
Ville Syrjälä
Intel OTC