On Wed, 15 Jun 2022 at 02:01, Emma Anholt emma@anholt.net wrote:
This is an SMMU for the adreno gpu, and adding this compatible lets the driver use per-fd page tables, which are required for security between GPU clients.
Signed-off-by: Emma Anholt emma@anholt.net
Tested with a full deqp-vk run on RB5, which did involve some iommu faults.
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index a92230bec1dd..483c0e0f1d1a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2513,7 +2513,7 @@ gpucc: clock-controller@3d90000 { };
adreno_smmu: iommu@3da0000 {
compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
compatible = "qcom,sm8250-smmu-500", "arm,mmu-500", "qcom,adreno-smmu";
I see that other dtsi files use a bit different order for the compatibility strings. They put "qcom,adreno-smmu" before "arm,mmu-500". Can we please follow them?
With that fixed: Reviewed-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org
reg = <0 0x03da0000 0 0x10000>; #iommu-cells = <2>; #global-interrupts = <2>;-- 2.36.1