On 2018-06-05 20:50, Rob Herring wrote:
On Tue, Jun 05, 2018 at 11:10:16AM +0530, Sandeep Panda wrote:
Document the bindings used for the sn65dsi86 DSI to eDP bridge.
Changes in v1:
- Rephrase the dt-binding descriptions to be more inline with
existing bindings (Andrzej Hajda).
- Add missing dt-binding that are parsed by corresponding driver (Andrzej Hajda).
Changes in v2:
- Remove edp panel specific dt-binding entries. Only keep bridge specific entries (Sean Paul).
- Remove custom-modes dt entry since its usage is removed from driver
also (Sean Paul).
- Remove is-pluggable dt entry since this will not be needed anymore
(Sean Paul).
Changes in v3:
- Remove irq-gpio dt entry and instead populate is an interrupt property (Rob Herring).
Changes in v4:
- Add link to bridge chip datasheet (Stephen Boyd)
- Add vpll and vcc regulator supply bindings (Stephen Boyd)
- Add ref clk optional dt binding (Stephen Boyd)
- Add gpio-controller optional dt binding (Stephen Boyd)
Changes in v5:
- Use clock property to specify the input refclk (Stephen Boyd).
- Update gpio cell and pwm cell numbers (Stephen Boyd).
Changes in v6:
- Add property to mention the lane mapping scheme and polarity
inversion (Stephen Boyd).
Changes in v7:
- Detail description of lane mapping scheme dt property (Andrzej Hajda/ Rob Herring).
- Removed HDP gpio binding, since the bridge uses IRQ signal to determine HPD, and IRQ property is already documented in binding.
Signed-off-by: Sandeep Panda spanda@codeaurora.org
.../bindings/display/bridge/ti,sn65dsi86.txt | 109 +++++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file mode 100644 index 0000000..33329f9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt @@ -0,0 +1,109 @@ +SN65DSI86 DSI to eDP bridge chip +--------------------------------
+This is the binding for Texas Instruments SN65DSI86 bridge. +http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65d...
+Required properties: +- compatible: Must be "ti,sn65dsi86" +- reg: i2c address of the chip, 0x2d as per datasheet +- enable-gpios: OF device-tree gpio specification for bridge_en pin (active high)
+- vccio-supply: A 1.8V supply that powers up the digital IOs. +- vpll-supply: A 1.8V supply that powers up the displayport PLL. +- vcca-supply: A 1.2V supply that powers up the analog circuits. +- vcc-supply: A 1.2V supply that powers up the digital core.
+Optional properties: +- interrupts: Specifier for the SN65DSI86 interrupt line.
+- ddc-i2c-bus: phandle of the I2C controller used for DDC EDID probing
+- gpio-controller: Marks the device has a GPIO controller. +- #gpio-cells : Should be two. The first cell is the pin number and
the second cell is used to specify flags.See ../../gpio/gpio.txt for more information.+- #pwm-cells : Should be one. See ../../pwm/pwm.txt for description of
the cell formats.+- clock-names: should be "refclk" +- clocks: Specification for input reference clock. The reference
clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.+- lane-mapping: Specification to describe the logical to physical lane
As I mentioned in v7, we already have a property for this. It's called 'data-lanes' and defined in media/video-interfaces.txt. Use that. If you need polarity too, then add a property for that. And add it to video-interfaces.txt.
The data-lanes property mentioned in media/video-interfaces.txt is referring to DSI/CSI lanes where assumption is clock lane is fixed at index 0. But here the we want to mention about eDP lanes which do not have dedicated clock lane. So can we still use the existing data-lanes property here?
mapping scheme and polarity inversion of eDP lanes on PCB.Each pair present at index n (where n lies between 0 and 3)describes the lane mapping of logical lane to physical lane nand the polarity(it should be either 1 or 0) of the physical lanen.
For example:lane-mapping = <2 1>,<1 0>,<3 1>,<0 0>;The above mapping describes that logical lane 2 is mapped tophysical lane 0 and polarity of physical lane 0 is inverted,logical lane 1 is mapped to physical lane 1 and polarity ofphysical lane 1 is normal, logical lane 3 is mapped to physicallane 2 and polarity of physical lane 2 is inverted, logical lane 0is mapped to physical lane 4 and polarity of physical lane 3 isnormal.
If this property is not mentioned then it is assumed that physicallanes 0 through 3 are mapped to logical lanes 0 through 3 andpolarity
of all physical lanes is normal.+Required nodes: +This device has two video ports. Their connections are modelled using the +OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
+- Video port 0 for DSI input +- Video port 1 for eDP output
+Example +-------
+edp-bridge@2d {
- compatible = "ti,sn65dsi86";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x2d>;
- enable-gpios = <&msmgpio 33 GPIO_ACTIVE_HIGH>;
- interrupt-parent = <&gpio3>;
- interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
- vccio-supply = <&pm8916_l17>;
- vcca-supply = <&pm8916_l6>;
- vpll-supply = <&pm8916_l17>;
- vcc-supply = <&pm8916_l6>;
- clock-names = "refclk";
- clocks = <&input_refclk>;
- lane-mapping = <0 0>, /* Logical lane 0 is routed to physical lane
0 (!inv) */
<1 1>, /* Logical lane 1 is routed to physical lane 1 (inv)*/
<2 0>, /* Logical lane 2 is routed to physical lane 2 (!inv)*/
<3 1>; /* Logical lane 3 is routed to physical lane 3 (inv)*/
- ports {
#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;edp_bridge_in: endpoint {remote-endpoint = <&dsi_out>;};};port@1 {reg = <1>;edp_bridge_out: endpoint {remote-endpoint = <&edp_panel_in>;};};- };
+}
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