On Fri, Aug 06, 2021 at 11:42:26AM +0200, Robert Foss wrote:
Hey Xin,
Thanks for implementing the suggestion so quickly.
Can you send this version of the patch out as v2? Versioning is important and both tools and processes break if different versions aren't submitted in different emails.
Hi Robert Foss, OK, thanks. Xin
On Fri, 6 Aug 2021 at 11:35, Xin Ji xji@analogixsemi.com wrote:
IVO panel require less input video clock variation than video clock variation in DP CTS spec.
This patch decreases the K value of ANX7625 which will shrink eDP Tx video clock variation to meet IVO panel's requirement.
Acked-by: Sam Ravnborg sam@ravnborg.org Signed-off-by: Xin Ji xji@analogixsemi.com
drivers/gpu/drm/bridge/analogix/anx7625.c | 24 ++++++++++++++++++++--- drivers/gpu/drm/bridge/analogix/anx7625.h | 4 +++- 2 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c index a3d82377066b..9b9e3984dd38 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.c +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c @@ -384,6 +384,25 @@ static int anx7625_odfc_config(struct anx7625_data *ctx, return ret; }
+/*
- The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz),
- anx7625 defined K ratio for matching MIPI input video clock and
- DP output video clock. Increase K value can match bigger video data
- variation. IVO panel has small variation than DP CTS spec, need
- decrease the K value.
- */
+static int anx7625_set_k_value(struct anx7625_data *ctx) +{
struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data;if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1)return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,MIPI_DIGITAL_ADJ_1, 0x3B);return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,MIPI_DIGITAL_ADJ_1, 0x3D);+}
static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) { struct device *dev = &ctx->client->dev; @@ -470,9 +489,8 @@ static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, (n & 0xff));
/* Diff */ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,MIPI_DIGITAL_ADJ_1, 0x3D);
anx7625_set_k_value(ctx); ret |= anx7625_odfc_config(ctx, post_divider - 1);diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.h b/drivers/gpu/drm/bridge/analogix/anx7625.h index 034c3840028f..6dcf64c703f9 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.h +++ b/drivers/gpu/drm/bridge/analogix/anx7625.h @@ -210,7 +210,9 @@ #define MIPI_VIDEO_STABLE_CNT 0x0A
#define MIPI_LANE_CTRL_10 0x0F -#define MIPI_DIGITAL_ADJ_1 0x1B +#define MIPI_DIGITAL_ADJ_1 0x1B +#define IVO_MID0 0x26 +#define IVO_MID1 0xCF
#define MIPI_PLL_M_NUM_23_16 0x1E
#define MIPI_PLL_M_NUM_15_8 0x1F
2.25.1