On 22 February 2011 18:25, Daniel Vetter daniel.vetter@ffwll.ch wrote:
It looks like gen2 has a peculiar interleaved 2-row inter-tile layout. Probably inherited from i81x which had 2kb tiles (which naturally fit an even-number-of-tile-rows scheme to fit onto 4kb pages). There is no other mention of this in any docs (also not in the Intel internal documention according to Chris Wilson).
Giving that lack of documentation, could you put some more comments in the code? so that nobody cleans out that "strange workaround" in 6 monthes...
@@ -215,6 +215,20 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) } }
- if (IS_GEN2(dev) ||
- (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
- tile_height = 32;
- else
- tile_height = 8;
- /* i8xx is strange: It has 2 interleaved rows of tiles, so needs an even
- * number of tile rows. */
- if (IS_GEN2(dev))
- tile_height *= 2;
- /* Size needs to be aligned to a full tile row */
- if (size & (tile_height * stride - 1))
- return false;
/* 965+ just needs multiples of tile width */ if (INTEL_INFO(dev)->gen >= 4) { if (stride & (tile_width - 1))