On Thu, Oct 21, 2021 at 07:56:24PM +0530, Ramalingam C wrote:
From: Matt Roper matthew.d.roper@intel.com
DG2 unifies render compression and media compression into a single format for the first time. The programming and buffer layout is supposed to match compression on older gen12 platforms, but the actual compression algorithm is different from any previous platform; as such, we need a new framebuffer modifier to represent buffers in this format, but otherwise we can re-use the existing gen12 compression driver logic.
DG2 clear color render compression uses Tile4 layout. Therefore, we need to define a new format modifier for uAPI to support clear color rendering.
Signed-off-by: Matt Roper matthew.d.roper@intel.com Signed-off-by: Mika Kahola mika.kahola@intel.com (v2) Signed-off-by: Juha-Pekka Heikkilä juha-pekka.heikkila@intel.com Signed-off-by: Ramalingam C ramalingam.c@intel.com cc: Simon Ser contact@emersion.fr Cc: Pekka Paalanen ppaalanen@gmail.com
drivers/gpu/drm/i915/display/intel_display.c | 3 ++ .../drm/i915/display/intel_display_types.h | 10 +++- drivers/gpu/drm/i915/display/intel_fb.c | 7 +++ .../drm/i915/display/skl_universal_plane.c | 49 +++++++++++++++++-- include/uapi/drm/drm_fourcc.h | 30 ++++++++++++ 5 files changed, 94 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 9b678839bf2b..2949fe9f5b9f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1013,6 +1013,9 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) cmd->pixel_format); case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
- case I915_FORMAT_MOD_F_TILED_DG2_RC_CCS:
- case I915_FORMAT_MOD_F_TILED_DG2_MC_CCS:
- case I915_FORMAT_MOD_F_TILED_DG2_RC_CCS_CC: return lookup_format_info(gen12_ccs_formats, ARRAY_SIZE(gen12_ccs_formats), cmd->pixel_format);
That seems not right. Flat CCS is invisible to the user so the format info should not include a CCS plane.