Hi,
On 14/02/2021 18:44, Jagan Teki wrote:
SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller IC's from Texas Instruments.
SN65DSI83 - Single Channel DSI to Single-link LVDS bridge SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
Right now the bridge driver is supporting Channel A with single link, so dt-bindings documented according to it.
Shouldn't it describe Dual-link LVDS already for SN65DSI84/85 and Dual Channel DSI for SN65DSI85 even if not implemented in the driver ?
Neil
Cc: Marek Vasut marex@denx.de Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Changes for v3:
- fixed Rob comments
- updated commit message and file name to support all chip variants
Changes for v2:
- none
.../bindings/display/bridge/ti,sn65dsi8x.yaml | 122 ++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml new file mode 100644 index 000000000000..7f9f8cd6e786 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi8x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: TI SN65DSI83/84/85 MIPI DSI to LVDS bridge bindings
+maintainers:
- Jagan Teki jagan@amarulasolutions.com
+description: |
- SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller
- IC's from Texas Instruments.
- SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
- SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
- SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
- Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and
- converts the formatted video data stream to a FlatLink compatible
- LVDS output operating at pixel clocks operating from 25 MHx to
- 154 MHz.
+properties:
- compatible:
- enum:
- ti,sn65dsi83
- ti,sn65dsi84
- reg:
- const: 0x2c
- enable-gpios:
- maxItems: 1
- description: GPIO specifier for bridge enable pin (active high).
- ports:
- $ref: /schemas/graph.yaml#/properties/ports
- properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: |
DSI Input. The remote endpoint phandle should be a
reference to a valid mipi_dsi_host device node.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: |
Video port for LVDS output (panel or connector).
- required:
- port@0
- port@1
+required:
- compatible
- reg
- enable-gpios
- ports
+additionalProperties: false
+examples:
- |
- #include <dt-bindings/gpio/gpio.h>
- dsi {
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_in: endpoint {
remote-endpoint = <<dc_ep0_out>;
};
};
port@1 {
reg = <1>;
dsi_out: endpoint {
remote-endpoint = <&bridge_in>;
data-lanes = <0 1>;
};
};
};
- };
- i2c6 {
#address-cells = <1>;
#size-cells = <0>;
bridge@2c {
compatible = "ti,sn65dsi84";
reg = <0x2c>;
enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
port@1 {
reg = <1>;
bridge_out: endpoint {
remote-endpoint = <&panel_in_lvds>;
};
};
};
};
- };