On Thu, May 16, 2013 at 6:50 AM, Jerome Glisse j.glisse@gmail.com wrote:
On Wed, May 15, 2013 at 2:22 PM, Andy Lutomirski luto@amacapital.net wrote:
On Wed, May 15, 2013 at 7:49 AM, Jerome Glisse j.glisse@gmail.com wrote:
On Tue, May 14, 2013 at 5:35 PM, Andy Lutomirski luto@amacapital.net wrote:
On Tue, May 14, 2013 at 6:37 AM, Jerome Glisse j.glisse@gmail.com wrote:
On Tue, May 14, 2013 at 8:58 AM, Alex Deucher alexdeucher@gmail.com wrote:
On Mon, May 13, 2013 at 7:58 PM, Andy Lutomirski luto@amacapital.net wrote: > Reviewed-by: Daniel Vetter daniel.vetter@ffwll.ch > Signed-off-by: Andy Lutomirski luto@amacapital.net
Reviewed-by: Alex Deucher alexander.deucher@amd.com
I believe it will break something but we could deal with the fallout once it happens.
FWIW, I'm running with this code on my machine right now using the radeon driver. Everything seems fine. If I build without MTRRs and without PAT, though, graphics are slow (as expected). So I think everything's okay.
--Andy
I am worried on p4 where i last see issue with that notably with agp.
Do you remember any details? It looks like PAT is enabled on Pentium 4 (i.e. famliy 0xF).
--Andy
No i don't, i think it was some pat errata on those about non real ram address and with agp. Memory is fuzzy. I might have time in couple of week to plug back my p4 and see how it behave.
Hmm. I couldn't find any PAT errata related to AGP.
Is it possible that the issue was that, if there was no MTRR covering the AGP aperture, that the mapping ended up as writeback? If so, I fixed that in this series.
In any case, if you see any problems, please let me know.
--Andy