On 2021-07-05 at 14:53:09 +0100, Matthew Auld wrote:
Convert all the drm_i915_gem_set_domain bits to proper kernel doc.
LGTM.
Reviewed-by: Ramalingam C ramalingam.c@intel.com
Suggested-by: Daniel Vetter daniel@ffwll.ch Signed-off-by: Matthew Auld matthew.auld@intel.com Cc: Thomas Hellström thomas.hellstrom@linux.intel.com Cc: Maarten Lankhorst maarten.lankhorst@linux.intel.com Cc: Tvrtko Ursulin tvrtko.ursulin@linux.intel.com Cc: Jordan Justen jordan.l.justen@intel.com Cc: Kenneth Graunke kenneth@whitecape.org Cc: Jason Ekstrand jason@jlekstrand.net Cc: Daniel Vetter daniel.vetter@ffwll.ch Cc: Ramalingam C ramalingam.c@intel.com
include/uapi/drm/i915_drm.h | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index a4faceeb8c32..6f94e5e7569a 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -880,14 +880,42 @@ struct drm_i915_gem_mmap_offset { __u64 extensions; };
+/**
- struct drm_i915_gem_set_domain - Adjust the objects write or read domain, in
- preparation for accessing the pages via some CPU domain.
- Specifying a new write or read domain will flush the object out of the
- previous domain(if required), before then updating the objects domain
- tracking with the new domain.
- Note this might involve waiting for the object first if it is still active on
- the GPU.
- Supported values for @read_domains and @write_domain:
- I915_GEM_DOMAIN_WC: Uncached write-combined domain
- I915_GEM_DOMAIN_CPU: CPU cache domain
- I915_GEM_DOMAIN_GTT: Mappable aperture domain
- All other domains are rejected.
- */
struct drm_i915_gem_set_domain {
- /** Handle for the object */
- /** @handle: Handle for the object. */ __u32 handle;
- /** New read domains */
- /**
* @read_domains: New read domains.*/
- /** New write domain */
- /**
* @write_domain: New write domain.** Note that having something in the write domain implies it's in the* read domain, and only that read domain.*/};
-- 2.26.3