The engine registers really shouldn't be touched during GuC submission as the GuC owns the registers. Don't call ring_is_idle and tie intel_engine_is_idle strickly the engine pm.
Because intel_engine_is_idle tied to the engine pm, retire requests before checking intel_engines_are_idle in gt_drop_caches, and lastly increase the timeout in gt_drop_caches for the intel_engines_are_idle check.
Signed-off-by: Matthew Brost matthew.brost@intel.com --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 13 +++++++++++++ drivers/gpu/drm/i915/i915_debugfs.c | 6 +++--- drivers/gpu/drm/i915/i915_drv.h | 2 +- 3 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index e34a61600c8c..591226b96201 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1226,6 +1226,9 @@ static bool ring_is_idle(struct intel_engine_cs *engine) { bool idle = true;
+ /* GuC submission shouldn't access HEAD & TAIL via MMIO */ + GEM_BUG_ON(intel_engine_uses_guc(engine)); + if (I915_SELFTEST_ONLY(!engine->mmio_base)) return true;
@@ -1292,6 +1295,16 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine) if (!i915_sched_engine_is_empty(engine->sched_engine)) return false;
+ /* + * We shouldn't touch engine registers with GuC submission as the GuC + * owns the registers. Let's tie the idle to engine pm, at worst this + * function sometimes will falsely report non-idle when idle during the + * delay to retire requests or with virtual engines and a request + * running on another instance within the same class / submit mask. + */ + if (intel_engine_uses_guc(engine)) + return false; + /* Ring stopped? */ return ring_is_idle(engine); } diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index d540dd8029d0..2639961504b5 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -867,13 +867,13 @@ gt_drop_caches(struct intel_gt *gt, u64 val) { int ret;
+ if (val & DROP_RETIRE || val & DROP_RESET_ACTIVE) + intel_gt_retire_requests(gt); + if (val & DROP_RESET_ACTIVE && wait_for(intel_engines_are_idle(gt), I915_IDLE_ENGINES_TIMEOUT)) intel_gt_set_wedged(gt);
- if (val & DROP_RETIRE) - intel_gt_retire_requests(gt); - if (val & (DROP_IDLE | DROP_ACTIVE)) { ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT); if (ret) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3cfa6effbb5f..aa359b8480cd 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -576,7 +576,7 @@ struct i915_gem_mm { u32 shrink_count; };
-#define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ +#define I915_IDLE_ENGINES_TIMEOUT (500) /* in ms */
unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915, u64 context);