Add get_ovl_name() and get_mgr_name() to dispc_ops and get rid of adhoc names here and there in the omapdrm code. This moves the names of hardware entities to omapdss side where they have to be when new omapdss backend drivers are introduced.
Signed-off-by: Jyri Sarha jsarha@ti.com --- drivers/gpu/drm/omapdrm/dss/dispc.c | 21 +++++++++++++++++++++ drivers/gpu/drm/omapdrm/dss/omapdss.h | 3 +++ drivers/gpu/drm/omapdrm/omap_crtc.c | 11 ++--------- drivers/gpu/drm/omapdrm/omap_irq.c | 19 +++++++------------ drivers/gpu/drm/omapdrm/omap_plane.c | 13 +++---------- 5 files changed, 36 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index 4e8f68e..070053f 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -680,6 +680,24 @@ void dispc_runtime_put(void) WARN_ON(r < 0 && r != -ENOSYS); }
+static const char *dispc_get_ovl_name(enum omap_plane_id plane) +{ + static const char *ovl_names[] = { + [OMAP_DSS_GFX] = "GFX", + [OMAP_DSS_VIDEO1] = "VID1", + [OMAP_DSS_VIDEO2] = "VID2", + [OMAP_DSS_VIDEO3] = "VID3", + [OMAP_DSS_WB] = "WB", + }; + + return ovl_names[plane]; +} + +static const char *dispc_get_mgr_name(enum omap_channel channel) +{ + return mgr_desc[channel].name; +} + static u32 dispc_mgr_get_vsync_irq(enum omap_channel channel) { return mgr_desc[channel].vsync_irq; @@ -4506,6 +4524,9 @@ static void dispc_errata_i734_wa(void) .get_num_ovls = dispc_get_num_ovls, .get_num_mgrs = dispc_get_num_mgrs,
+ .get_ovl_name = dispc_get_ovl_name, + .get_mgr_name = dispc_get_mgr_name, + .get_memory_bandwidth_limit = dispc_get_memory_bandwidth_limit,
.mgr_enable = dispc_mgr_enable, diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h index f8f83e8..d7ed1a4 100644 --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h @@ -691,6 +691,9 @@ struct dispc_ops { int (*get_num_ovls)(void); int (*get_num_mgrs)(void);
+ const char *(*get_ovl_name)(enum omap_plane_id plane); + const char *(*get_mgr_name)(enum omap_channel channel); + u32 (*get_memory_bandwidth_limit)(void);
void (*mgr_enable)(enum omap_channel channel, bool enable); diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index 1b8154e..fee8a63 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -662,13 +662,6 @@ static void omap_crtc_reset(struct drm_crtc *crtc) * Init and Cleanup */
-static const char *channel_names[] = { - [OMAP_DSS_CHANNEL_LCD] = "lcd", - [OMAP_DSS_CHANNEL_DIGIT] = "tv", - [OMAP_DSS_CHANNEL_LCD2] = "lcd2", - [OMAP_DSS_CHANNEL_LCD3] = "lcd3", -}; - void omap_crtc_pre_init(void) { memset(omap_crtcs, 0, sizeof(omap_crtcs)); @@ -696,7 +689,7 @@ struct drm_crtc *omap_crtc_init(struct drm_device *dev, channel = out->dispc_channel; omap_dss_put_device(out);
- DBG("%s", channel_names[channel]); + DBG("%s", priv->dispc_ops->get_mgr_name(channel));
/* Multiple displays on same channel is not allowed */ if (WARN_ON(omap_crtcs[channel] != NULL)) @@ -711,7 +704,7 @@ struct drm_crtc *omap_crtc_init(struct drm_device *dev, init_waitqueue_head(&omap_crtc->pending_wait);
omap_crtc->channel = channel; - omap_crtc->name = channel_names[channel]; + omap_crtc->name = priv->dispc_ops->get_mgr_name(channel);
ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL, &omap_crtc_funcs, NULL); diff --git a/drivers/gpu/drm/omapdrm/omap_irq.c b/drivers/gpu/drm/omapdrm/omap_irq.c index 53ba424..b0f6850 100644 --- a/drivers/gpu/drm/omapdrm/omap_irq.c +++ b/drivers/gpu/drm/omapdrm/omap_irq.c @@ -144,15 +144,10 @@ static void omap_irq_fifo_underflow(struct omap_drm_private *priv, { static DEFINE_RATELIMIT_STATE(_rs, DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST); - static const struct { - const char *name; - u32 mask; - } sources[] = { - { "gfx", DISPC_IRQ_GFX_FIFO_UNDERFLOW }, - { "vid1", DISPC_IRQ_VID1_FIFO_UNDERFLOW }, - { "vid2", DISPC_IRQ_VID2_FIFO_UNDERFLOW }, - { "vid3", DISPC_IRQ_VID3_FIFO_UNDERFLOW }, - }; + static const u32 irqbits[] = { DISPC_IRQ_GFX_FIFO_UNDERFLOW, + DISPC_IRQ_VID1_FIFO_UNDERFLOW, + DISPC_IRQ_VID2_FIFO_UNDERFLOW, + DISPC_IRQ_VID3_FIFO_UNDERFLOW };
const u32 mask = DISPC_IRQ_GFX_FIFO_UNDERFLOW | DISPC_IRQ_VID1_FIFO_UNDERFLOW @@ -172,9 +167,9 @@ static void omap_irq_fifo_underflow(struct omap_drm_private *priv,
DRM_ERROR("FIFO underflow on ");
- for (i = 0; i < ARRAY_SIZE(sources); ++i) { - if (sources[i].mask & irqstatus) - pr_cont("%s ", sources[i].name); + for (i = 0; i < ARRAY_SIZE(irqbits); ++i) { + if (irqbits[i] & irqstatus) + pr_cont("%s ", priv->dispc_ops->get_ovl_name(i)); }
pr_cont("(0x%08x)\n", irqstatus); diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c index 7d789d1..6f9d9ef 100644 --- a/drivers/gpu/drm/omapdrm/omap_plane.c +++ b/drivers/gpu/drm/omapdrm/omap_plane.c @@ -239,13 +239,6 @@ static int omap_plane_atomic_get_property(struct drm_plane *plane, .atomic_get_property = omap_plane_atomic_get_property, };
-static const char *plane_id_to_name[] = { - [OMAP_DSS_GFX] = "gfx", - [OMAP_DSS_VIDEO1] = "vid1", - [OMAP_DSS_VIDEO2] = "vid2", - [OMAP_DSS_VIDEO3] = "vid3", -}; - static const enum omap_plane_id plane_idx_to_id[] = { OMAP_DSS_GFX, OMAP_DSS_VIDEO1, @@ -272,7 +265,7 @@ struct drm_plane *omap_plane_init(struct drm_device *dev,
id = plane_idx_to_id[idx];
- DBG("%s: type=%d", plane_id_to_name[id], type); + DBG("%s: type=%d", priv->dispc_ops->get_ovl_name(id), type);
omap_plane = kzalloc(sizeof(*omap_plane), GFP_KERNEL); if (!omap_plane) @@ -282,7 +275,7 @@ struct drm_plane *omap_plane_init(struct drm_device *dev, for (nformats = 0; formats[nformats]; ++nformats) ; omap_plane->id = id; - omap_plane->name = plane_id_to_name[id]; + omap_plane->name = priv->dispc_ops->get_ovl_name(id);
plane = &omap_plane->base;
@@ -301,7 +294,7 @@ struct drm_plane *omap_plane_init(struct drm_device *dev,
error: dev_err(dev->dev, "%s(): could not create plane: %s\n", - __func__, plane_id_to_name[id]); + __func__, priv->dispc_ops->get_ovl_name(id));
kfree(omap_plane); return NULL;