From: Frieder Schrempf frieder.schrempf@kontron.de
On i.MX8MM there is an interrupt getting triggered immediately after requesting the IRQ, which leads to a stall as the handler accesses the GPU registers whithout the clock being enabled.
Enabling the clocks briefly seems to clear the IRQ state, so we do this before requesting the IRQ.
Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de --- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 29 ++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index a31eeff2b297..23877c1f150a 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -1775,13 +1775,6 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev) return gpu->irq; }
- err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0, - dev_name(gpu->dev), gpu); - if (err) { - dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); - return err; - } - /* Get Clocks: */ gpu->clk_reg = devm_clk_get(&pdev->dev, "reg"); DBG("clk_reg: %p", gpu->clk_reg); @@ -1805,6 +1798,28 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev) gpu->clk_shader = NULL; gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
+ /* + * On i.MX8MM there is an interrupt getting triggered immediately + * after requesting the IRQ, which leads to a stall as the handler + * accesses the GPU registers whithout the clock being enabled. + * Enabling the clocks briefly seems to clear the IRQ state, so we do + * this here before requesting the IRQ. + */ + err = etnaviv_gpu_clk_enable(gpu); + if (err) + return err; + + err = etnaviv_gpu_clk_disable(gpu); + if (err) + return err; + + err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0, + dev_name(gpu->dev), gpu); + if (err) { + dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); + return err; + } + /* TODO: figure out max mapped size */ dev_set_drvdata(dev, gpu);