For RK3399's GRF module, if we want to operate the graphic related grf registers, we need to enable the pclk_vio_grf which supply power for VIO GRF IOs, so it's better to introduce an optional grf clock in driver.
Signed-off-by: Yakir Yang ykk@rock-chips.com Reviewed-by: Douglas Anderson dianders@chromium.org Reviewed-by: Tomasz Figa tomasz.figa@chromium.com --- Changes in v4: - Add reviewed flag from Doug. - Add reviewed flag from Tomasz. - Fix compiled error, sorry. "dp->cgfclk" --> 'dp->grfclk' - Check the the error code properly, 'EPROBE_DEFER' should be returned, 'ENOENT' should assign a NULL point to grfclk, other errors should be regarded as failed. (Tomasz, Doug, reviewed at Google Gerrit) [https://chromium-review.googlesource.com/#/c/351821/20/drivers/gpu/drm/rockc...] - Add the document about optional 'grf' clock (Tomasz, Doug, reviewed at Google Gerrit) [https://chromium-review.googlesource.com/#/c/351821/]
Changes in v3: - Add this patch in v3
.../display/rockchip/analogix_dp-rockchip.txt | 6 ++++++ drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 23 +++++++++++++++++++--- 2 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt index 726c945..0b39256 100644 --- a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt @@ -28,6 +28,12 @@ Required properties: Port 0: contained 2 endpoints, connecting to the output of vop. Port 1: contained 1 endpoint, connecting to the input of panel.
+Optional property for different chips: +- clocks: from common clock binding: handle to grf_vio clock. + +- clock-names: from common clock binding: + Required elements: "grf" + For the below properties, please refer to Analogix DP binding document: * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt - phys (required) diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index 850edc4..e81e19a 100644 --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c @@ -64,6 +64,7 @@ struct rockchip_dp_device { struct drm_display_mode mode;
struct clk *pclk; + struct clk *grfclk; struct regmap *grf; struct reset_control *rst;
@@ -160,11 +161,17 @@ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
- ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val); - if (ret != 0) { - dev_err(dp->dev, "Could not write to GRF: %d\n", ret); + ret = clk_prepare_enable(dp->grfclk); + if (ret < 0) { + dev_err(dp->dev, "failed to enable grfclk %d\n", ret); return; } + + ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val); + if (ret != 0) + dev_err(dp->dev, "Could not write to GRF: %d\n", ret); + + clk_disable_unprepare(dp->grfclk); }
static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder) @@ -234,6 +241,16 @@ static int rockchip_dp_init(struct rockchip_dp_device *dp) return PTR_ERR(dp->grf); }
+ dp->grfclk = devm_clk_get(dev, "grf"); + if (PTR_ERR(dp->grfclk) == -ENOENT) { + dp->grfclk = NULL; + } else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) { + return -EPROBE_DEFER; + } else if (IS_ERR(dp->grfclk)) { + dev_err(dev, "failed to get grf clock\n"); + return PTR_ERR(dp->grfclk); + } + dp->pclk = devm_clk_get(dev, "pclk"); if (IS_ERR(dp->pclk)) { dev_err(dev, "failed to get pclk property\n");