Re: [PATCH 04/14] dt-bindings: display: bridge: Add i.MX8qm/qxp pixel combiner binding

On Thu, Dec 17, 2020 at 05:59:23PM +0800, Liu Ying wrote:

This patch adds bindings for i.MX8qm/qxp pixel combiner.

Signed-off-by: Liu Ying victor.liu@nxp.com

.../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 160 +++++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml new file mode 100644 index 00000000..bacacd8 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml... +$schema: http://devicetree.org/meta-schemas/core.yaml#

+title: Freescale i.MX8qm/qxp Pixel Combiner

+maintainers:

• • Liu Ying victor.liu@nxp.com

+description: |

• The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
• single display controller and manipulates the two streams to support a number
• of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as
• either one screen, two screens, or virtual screens. The pixel combiner is
• also responsible for generating some of the control signals for the pixel link
• output channel.

+properties:

• compatible:
• enum:

•  - fsl,imx8qm-pixel-combiner
  

•  - fsl,imx8qxp-pixel-combiner
  

• "#address-cells":
• const: 1
• "#size-cells":
• const: 0
• reg:
• maxItems: 1
• clocks:
• maxItems: 1
• clock-names:
• const: apb
• power-domains:
• maxItems: 1

+patternProperties:

• "^channel@[0-1]$":
• type: object
• description: Represents a display stream of pixel combiner.
• properties:

•  "#address-cells":
  

•    const: 1
  

•  "#size-cells":
  

•    const: 0
  

•  reg:
  

•    description: The display stream index.
  

•    oneOf:
  

•      - const: 0
  

•      - const: 1
  

enum: [ 0, 1 ]

•  port@0:
  

•    type: object
  

•    description: Input endpoint of the display stream.
  

•    properties:
  

•      reg:
  

•        const: 0
  

•    required:
  

•      - reg
  

You can drop 'reg' parts. That's going to get covered by the graph schema.

•  port@1:
  

•    type: object
  

•    description: Output endpoint of the display stream.
  

•    properties:
  

•      reg:
  

•        const: 1
  

•    required:
  

•      - reg
  

• required:

•  - "#address-cells"
  

•  - "#size-cells"
  

•  - reg
  

•  - port@0
  

•  - port@1
  

• additionalProperties: false

+required:

• • compatible
• • "#address-cells"
• • "#size-cells"
• • reg
• • clocks
• • clock-names
• • power-domains

+additionalProperties: false

+examples:

• • |
• #include <dt-bindings/clock/imx8-lpcg.h>
• #include <dt-bindings/firmware/imx/rsrc.h>
• pixel-combiner@56020000 {

•    compatible = "fsl,imx8qxp-pixel-combiner";
  

•    #address-cells = <1>;
  

•    #size-cells = <0>;
  

•    reg = <0x56020000 0x10000>;
  

•    clocks = <&dc0_pixel_combiner_lpcg IMX_LPCG_CLK_4>;
  

•    clock-names = "apb";
  

•    power-domains = <&pd IMX_SC_R_DC_0>;
  

•    channel@0 {
  

•        #address-cells = <1>;
  

•        #size-cells = <0>;
  

•        reg = <0>;
  

•        port@0 {
  

•            reg = <0>;
  

•            dc0_pixel_combiner_ch0_dc0_dpu_disp0: endpoint {
  

•                remote-endpoint = <&dc0_dpu_disp0_dc0_pixel_combiner_ch0>;
  

•            };
  

•        };
  

•        port@1 {
  

•            reg = <1>;
  

•            dc0_pixel_combiner_ch0_dc0_pixel_link0: endpoint {
  

•                remote-endpoint = <&dc0_pixel_link0_dc0_pixel_combiner_ch0>;
  

•            };
  

•        };
  

•    };
  

•    channel@1 {
  

•        #address-cells = <1>;
  

•        #size-cells = <0>;
  

•        reg = <1>;
  

•        port@0 {
  

•            reg = <0>;
  

•            dc0_pixel_combiner_ch1_dc0_dpu_disp1: endpoint {
  

•                remote-endpoint = <&dc0_dpu_disp1_dc0_pixel_combiner_ch1>;
  

•            };
  

•        };
  

•        port@1 {
  

•            reg = <1>;
  

•            dc0_pixel_combiner_ch1_dc0_pixel_link1: endpoint {
  

•                remote-endpoint = <&dc0_pixel_link1_dc0_pixel_combiner_ch1>;
  

•            };
  

•        };
  

•    };
  

• };

-- 2.7.4