27.10.2020 11:54, Krzysztof Kozlowski пишет:
On Mon, Oct 26, 2020 at 01:16:47AM +0300, Dmitry Osipenko wrote:
Tegra20 External Memory Controller talks to DRAM chips and it needs to be reprogrammed when memory frequency changes. Tegra Memory Controller sits behind EMC and these controllers are tightly coupled. This patch adds the new phandle property which allows to properly express connection of EMC and MC hardware in a device-tree, it also put the Tegra20 EMC binding on par with Tegra30+ EMC bindings, which is handy to have.
Signed-off-by: Dmitry Osipenko digetx@gmail.com
.../bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index 567cffd37f3f..1b0d4417aad8 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -12,6 +12,7 @@ Properties: irrespective of ram-code configuration.
- interrupts : Should contain EMC General interrupt.
- clocks : Should contain EMC clock.
+- nvidia,memory-controller : Phandle of the Memory Controller node.
It looks like you adding a required property which is an ABI break.
The T20 EMC driver is unused so far in upstream and it will become used only once this series is applied. Hence it's fine to change the ABI.