From: Arnd Bergmann arnd@arndb.de
The new display synchronization code caused a regression on all 32-bit architectures:
ld.lld: error: undefined symbol: __aeabi_uldivmod
referenced by dce_clock_source.c gpu/drm/amd/display/dc/dce/dce_clock_source.o:(get_pixel_clk_frequency_100hz) in archive drivers/built-in.a
ld.lld: error: undefined symbol: __aeabi_ldivmod
referenced by dc_resource.c gpu/drm/amd/display/dc/core/dc_resource.o:(resource_are_vblanks_synchronizable) in archive drivers/built-in.a referenced by dc_resource.c gpu/drm/amd/display/dc/core/dc_resource.o:(resource_are_vblanks_synchronizable) in archive drivers/built-in.a referenced by dc_resource.c gpu/drm/amd/display/dc/core/dc_resource.o:(resource_are_vblanks_synchronizable) in archive drivers/built-in.a
This is not a fast path, so the use of an explicit div_u64/div_s64 seems appropriate.
Fixes: 77a2b7265f20 ("drm/amd/display: Synchronize displays with different timings") Signed-off-by: Arnd Bergmann arnd@arndb.de --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 12 ++++++------ .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 6 +++--- 2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 0241c9d96d7a..49214c59c836 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -441,15 +441,15 @@ bool resource_are_vblanks_synchronizable( if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/ stream2->timing.v_total > 60) return false; - frame_time_diff = (int64_t)10000 * + frame_time_diff = div_s64(10000ll * stream1->timing.h_total * stream1->timing.v_total * - stream2->timing.pix_clk_100hz / - stream1->timing.pix_clk_100hz / - stream2->timing.h_total / - stream2->timing.v_total; + stream2->timing.pix_clk_100hz, + stream1->timing.pix_clk_100hz * + stream2->timing.h_total * + stream2->timing.v_total); for (i = 0; i < rr_count; i++) { - int64_t diff = (frame_time_diff * base60_refresh_rates[i]) / 10 - 10000; + int64_t diff = div_s64(frame_time_diff * base60_refresh_rates[i], 10) - 10000;
if (diff < 0) diff = -diff; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 6f47f9bab5ee..85ed6f2c9647 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -1013,9 +1013,9 @@ static bool get_pixel_clk_frequency_100hz( * not be programmed equal to DPREFCLK */ modulo_hz = REG_READ(MODULO[inst]); - *pixel_clk_khz = ((uint64_t)clock_hz* - clock_source->ctx->dc->clk_mgr->dprefclk_khz*10)/ - modulo_hz; + *pixel_clk_khz = div_u64((uint64_t)clock_hz * 10 * + clock_source->ctx->dc->clk_mgr->dprefclk_khz, + modulo_hz); } else { /* NOTE: There is agreement with VBIOS here that MODULO is * programmed equal to DPREFCLK, in which case PHASE will be