Just add the extra PCI-ID to the existing fixup.
Signed-off-by: Christian König christian.koenig@amd.com --- arch/x86/pci/fixup.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c index aa8b20e..3eebb0e 100644 --- a/arch/x86/pci/fixup.c +++ b/arch/x86/pci/fixup.c @@ -639,7 +639,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff); * configuring host bridge windows using the _PRS and _SRS methods. * * But this is rarely implemented, so we manually enable a large 64bit BAR for - * PCIe device on AMD Family 15h (Models 00h-1fh, 30h-3fh) Processors here. + * PCIe device on AMD Family 15h (Models 00h-1fh, 30h-3fh, 60h-6fh) Processors + * here. */ static void pci_amd_enable_64bit_bar(struct pci_dev *dev) { @@ -697,6 +698,7 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev) } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
#endif