Specify TTM_PL_FLAG_UNCACHED when allocating GPFIFOs and fences to allow them to be safely accessed by the kernel without being synced on non-coherent architectures.
Signed-off-by: Alexandre Courbot acourbot@nvidia.com --- drm/nouveau_chan.c | 2 +- drm/nv84_fence.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drm/nouveau_chan.c b/drm/nouveau_chan.c index 77c81d6b45ee..0f3da86840f2 100644 --- a/drm/nouveau_chan.c +++ b/drm/nouveau_chan.c @@ -102,7 +102,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, chan->drm = drm;
/* allocate memory for dma push buffer */ - target = TTM_PL_FLAG_TT; + target = TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED; if (nouveau_vram_pushbuf) target = TTM_PL_FLAG_VRAM;
diff --git a/drm/nv84_fence.c b/drm/nv84_fence.c index d6c6c87c3f07..4d79be7558d8 100644 --- a/drm/nv84_fence.c +++ b/drm/nv84_fence.c @@ -246,8 +246,8 @@ nv84_fence_create(struct nouveau_drm *drm)
if (ret == 0) ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, - TTM_PL_FLAG_TT, 0, 0, NULL, NULL, - &priv->bo_gart); + TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED, 0, + 0, NULL, NULL, &priv->bo_gart); if (ret == 0) { ret = nouveau_bo_pin(priv->bo_gart, TTM_PL_FLAG_TT); if (ret == 0) {