Hi Venkateshwar,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm/drm-next] [also build test WARNING on linus/master v5.19-rc2 next-20220617] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Venkateshwar-Rao-Gannavarapu/... base: git://anongit.freedesktop.org/drm/drm drm-next config: riscv-randconfig-s031-20220619 (https://download.01.org/0day-ci/archive/20220619/202206191404.Z1X0BOIH-lkp@i...) compiler: riscv32-linux-gcc (GCC) 11.3.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # apt-get install sparse # sparse version: v0.6.4-30-g92122700-dirty # https://github.com/intel-lab-lkp/linux/commit/28aa62ffdc1901029bf75961166f4e... git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Venkateshwar-Rao-Gannavarapu/Add-Xilinx-DSI-Tx-subsystem-DRM-driver/20220616-222008 git checkout 28aa62ffdc1901029bf75961166f4ebba948b9b7 # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=riscv SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable Reported-by: kernel test robot yujie.liu@intel.com
sparse warnings: (new ones prefixed by >>)
drivers/gpu/drm/xlnx/xlnx_dsi.c:218:27: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct xlnx_dsi *dsi @@ got void [noderef] __iomem *iomem @@
drivers/gpu/drm/xlnx/xlnx_dsi.c:218:27: sparse: expected struct xlnx_dsi *dsi drivers/gpu/drm/xlnx/xlnx_dsi.c:218:27: sparse: got void [noderef] __iomem *iomem
drivers/gpu/drm/xlnx/xlnx_dsi.c:256:9: sparse: sparse: statement expected after case label
vim +256 drivers/gpu/drm/xlnx/xlnx_dsi.c
28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 179 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 180 static void 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 181 xlnx_dsi_bridge_enable(struct drm_bridge *bridge, 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 182 struct drm_bridge_state *old_bridge_state) 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 183 { 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 184 struct xlnx_dsi *dsi = bridge_to_dsi(bridge); 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 185 struct drm_atomic_state *state = old_bridge_state->base.state; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 186 struct drm_connector *connector; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 187 struct drm_crtc *crtc; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 188 const struct drm_crtc_state *crtc_state; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 189 const struct drm_display_mode *mode; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 190 u32 reg, video_mode; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 191 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 192 connector = drm_atomic_get_new_connector_for_encoder(state, 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 193 bridge->encoder); 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 194 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 195 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 196 mode = &crtc_state->adjusted_mode; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 197 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 198 reg = xlnx_dsi_read(dsi, XDSI_PCR); 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 199 video_mode = (reg & XDSI_PCR_VIDEOMODE_MASK) >> XDSI_PCR_VIDEOMODE_SHIFT; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 200 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 201 if (!video_mode && (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)) { 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 202 reg = XDSI_TIME1_HSA(mode->hsync_end - 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 203 mode->hsync_start); 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 204 xlnx_dsi_write(dsi, XDSI_TIME1, reg); 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 205 } 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 206 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 207 reg = XDSI_TIME4_VFP(mode->vsync_start - mode->vdisplay) | 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 208 XDSI_TIME4_VBP(mode->vtotal - mode->vsync_end) | 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 209 XDSI_TIME4_VSA(mode->vsync_end - mode->vsync_start); 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 210 xlnx_dsi_write(dsi, XDSI_TIME4, reg); 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 211 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 212 reg = XDSI_TIME3_HFP(mode->hsync_start - mode->hdisplay) | 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 213 XDSI_TIME3_HBP(mode->htotal - mode->hsync_end); 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 214 xlnx_dsi_write(dsi, XDSI_TIME3, reg); 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 215 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 216 reg = XDSI_TIME2_HACT(mode->hdisplay * dsi->mul_factor / 100) | 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 217 XDSI_TIME2_VACT(mode->vdisplay); 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 @218 xlnx_dsi_write(dsi->iomem, XDSI_TIME2, reg); 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 219 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 220 xlnx_dsi_write(dsi, XDSI_PCR, XDSI_PCR_VIDEOMODE(BIT(0))); 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 221 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 222 /* Enable Core */ 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 223 reg = xlnx_dsi_read(dsi, XDSI_CCR); 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 224 reg |= XDSI_CCR_COREENB; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 225 xlnx_dsi_write(dsi, XDSI_CCR, reg); 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 226 } 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 227 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 228 #define MAX_INPUT_SEL_FORMATS 3 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 229 static u32 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 230 *xlnx_dsi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 231 struct drm_bridge_state *bridge_state, 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 232 struct drm_crtc_state *crtc_state, 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 233 struct drm_connector_state *conn_state, 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 234 u32 output_fmt, 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 235 unsigned int *num_input_fmts) 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 236 { 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 237 u32 *input_fmts; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 238 unsigned int i = 0; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 239 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 240 *num_input_fmts = 0; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 241 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), GFP_KERNEL); 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 242 if (!input_fmts) 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 243 return NULL; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 244 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 245 switch (output_fmt) { 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 246 case MEDIA_BUS_FMT_FIXED: 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 247 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 248 break; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 249 case MEDIA_BUS_FMT_RGB666_1X18: 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 250 input_fmts[i++] = MEDIA_BUS_FMT_RGB666_1X18; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 251 break; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 252 case MEDIA_BUS_FMT_RGB565_1X16: 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 253 input_fmts[i++] = MEDIA_BUS_FMT_RGB565_1X16; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 254 break; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 255 default: /* define */ 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 @256 } 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 257 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 258 *num_input_fmts = i; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 259 if (*num_input_fmts == 0) { 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 260 kfree(input_fmts); 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 261 input_fmts = NULL; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 262 } 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 263 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 264 return input_fmts; 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 265 } 28aa62ffdc1901 Venkateshwar Rao Gannavarapu 2022-06-16 266