On Fri, Aug 16, 2013 at 9:31 PM, Ian Romanick idr@freedesktop.org wrote:
On 08/14/2013 01:19 AM, Sedat Dilek wrote:
AFAICS, there are more updates needed to be in sync with recent kernel-drm.
I fell over the misspelling when digging into an issue in Linux-next. The spelling should be consistent in kernel-drm, libdrm, intel-ddx, etc. Here, I had a look especially at the defined macros (defines).
Signed-off-by: Sedat Dilek sedat.dilek@gmail.com
This should get Chris's ok before committing, but
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com
Thanks for the review.
Just FYI: For intel-ddx... the misspellings were fixed already.
- Sedat -
[1] http://cgit.freedesktop.org/xorg/driver/xf86-video-intel/commit/?id=6bd89715...
include/drm/i915_drm.h | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h index aa983f3..61a8407 100644 --- a/include/drm/i915_drm.h +++ b/include/drm/i915_drm.h @@ -195,8 +195,8 @@ typedef struct _drm_i915_sarea { #define DRM_I915_GEM_WAIT 0x2c #define DRM_I915_GEM_CONTEXT_CREATE 0x2d #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e -#define DRM_I915_GEM_SET_CACHEING 0x2f -#define DRM_I915_GEM_GET_CACHEING 0x30 +#define DRM_I915_GEM_SET_CACHING 0x2f +#define DRM_I915_GEM_GET_CACHING 0x30 #define DRM_I915_REG_READ 0x31
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) @@ -222,8 +222,8 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE
- DRM_I915_GEM_PIN, struct drm_i915_gem_pin) #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE +
DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE
- DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
-#define DRM_IOCTL_I915_GEM_SET_CACHEING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHEING, struct drm_i915_gem_cacheing) -#define DRM_IOCTL_I915_GEM_GET_CACHEING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHEING, struct drm_i915_gem_cacheing) +#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) +#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE
- DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE +
DRM_I915_GEM_THROTTLE) #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) @@ -706,21 +706,22 @@ struct drm_i915_gem_busy { __u32 busy; };
-#define I915_CACHEING_NONE 0 -#define I915_CACHEING_CACHED 1 +#define I915_CACHING_NONE 0 +#define I915_CACHING_CACHED 1 +#define I915_CACHING_DISPLAY 2
-struct drm_i915_gem_cacheing { +struct drm_i915_gem_caching { /**
* Handle of the buffer to set/get the cacheing level of. */
* Handle of the buffer to set/get the caching level of. */ __u32 handle; /** * Cacheing level to apply or return value *
* bits0-15 are for generic cacheing control (i.e. the abovedefined
* bits0-15 are for generic caching control (i.e. the abovedefined * values). bits16-31 are reserved for platform-specific variations * (e.g. l3$ caching on gen7). */
__u32 cacheing;
__u32 caching;};
#define I915_TILING_NONE 0