On Fri, Nov 15, 2013 at 12:55 PM, Marek Olšák maraeo@gmail.com wrote:
From: Michel Dänzer michel.daenzer@amd.com
Bug fixes and simplification by Marek. We have to use the tile index of 0 for non-MSAA depth-stencil after all.
Signed-off-by: Marek Olšák marek.olsak@amd.com
include/drm/radeon_drm.h | 11 + radeon/radeon_surface.c | 620 ++++++++++++++++++++++++++++++++++++++++++++++- radeon/radeon_surface.h | 1 + 3 files changed, 623 insertions(+), 9 deletions(-)
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h index d1bebf5..96ea555 100644 --- a/include/drm/radeon_drm.h +++ b/include/drm/radeon_drm.h @@ -979,6 +979,10 @@ struct drm_radeon_cs { #define RADEON_INFO_RING_WORKING 0x15 /* SI tile mode array */ #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16 +/* query if CP DMA is supported on the compute ring */ +#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 +/* CIK macrotile mode array */ +#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18
struct drm_radeon_info { uint32_t request; @@ -1004,6 +1008,13 @@ struct drm_radeon_info { #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3 #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2
+#define CIK_TILE_MODE_COLOR_2D 14 +#define CIK_TILE_MODE_COLOR_2D_SCANOUT 10 +#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_64 0 +#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_128 1 +#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_256 2 +#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_512 3 +#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_ROW_SIZE 4 #define CIK_TILE_MODE_DEPTH_STENCIL_1D 5
#endif diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 56e2e4a..927a21e 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -26,6 +26,8 @@
- Authors:
Jérôme Glisse <jglisse@redhat.com>*/ +#include <stdbool.h> +#include <assert.h> #include <errno.h> #include <stdio.h> #include <stdlib.h> @@ -95,6 +97,8 @@ struct radeon_hw_info { unsigned allow_2d; /* apply to si */ uint32_t tile_mode_array[32];
- /* apply to cik */
- uint32_t macrotile_mode_array[16];
};
struct radeon_surface_manager { @@ -1382,16 +1386,10 @@ static int si_surface_sanity(struct radeon_surface_manager *surf_man, break; case RADEON_SURF_MODE_1D: if (surf->flags & RADEON_SURF_SBUFFER) {
if (surf_man->family >= CHIP_BONAIRE)*stencil_tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D;else*stencil_tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
*stencil_tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D; } if (surf->flags & RADEON_SURF_ZBUFFER) {
if (surf_man->family >= CHIP_BONAIRE)*tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D;else*tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
*tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D; } else if (surf->flags & RADEON_SURF_SCANOUT) { *tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT; } else {@@ -1788,6 +1786,604 @@ static int si_surface_best(struct radeon_surface_manager *surf_man,
/* ===========================================================================
- Sea Islands family
- */
+#define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f) +#define CIK__PIPE_CONFIG__ADDR_SURF_P2 0 +#define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4 +#define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5 +#define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6 +#define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7 +#define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8 +#define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9 +#define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10 +#define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11 +#define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12 +#define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13 +#define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
Hawaii adds 2 P16 pipe formats:
#define ADDR_SURF_P16_32X32_8X16 0x10 #define ADDR_SURF_P16_32X32_16X16 0x11
Might be worth handling them in this patch or a follow up patch so we don't forget. Other than that both patches are:
Reviewed-by: Alex Deucher alexander.deucher@amd.com