On Tue, Sep 26, 2017 at 06:59:17AM +0000, Chen-Yu Tsai wrote:
The HDMI controller found in the A31 SoCs is slightly different from the one already supported, which is found in the A10s:
Need different initial values for the PLL related registers
Different behavior of the DDC and TMDS clocks
Different register layout for the DDC portion
Separate DDC parent clock
This patch adds support for it.
Signed-off-by: Chen-Yu Tsai wens@csie.org
Acked-by: Maxime Ripard maxime.ripard@free-electrons.com
Thanks! Maxime