On Tue, Feb 11, 2020 at 8:44 AM Rob Clark robdclark@gmail.com wrote:
On Mon, Feb 10, 2020 at 9:58 PM harigovi@codeaurora.org wrote:
On 2020-02-07 19:40, Jeffrey Hugo wrote:
On Fri, Feb 7, 2020 at 5:38 AM harigovi@codeaurora.org wrote:
On 2020-02-06 20:29, Jeffrey Hugo wrote:
On Thu, Feb 6, 2020 at 2:13 AM Harigovindan P harigovi@codeaurora.org wrote:
For a given byte clock, if VCO recalc value is exactly same as vco set rate value, vco_set_rate does not get called assuming VCO is already set to required value. But Due to GDSC toggle, VCO values are erased in the HW. To make sure VCO is programmed correctly, we forcefully call set_rate from vco_prepare.
Is this specific to certain SoCs? I don't think I've observed this.
As far as Qualcomm SOCs are concerned, since pll is analog and the value is directly read from hardware if we get recalc value same as set rate value, the vco_set_rate will not be invoked. We checked in our idp device which has the same SOC but it works there since the rates are different.
This doesn't seem to be an answer to my question. What Qualcomm SoCs does this issue apply to? Everything implementing the 10nm pll? One specific SoC? I don't believe I've seen this on MSM8998, nor SDM845, so I'm interested to know what is the actual impact here. I don't see an "IDP" SoC in the IP catalog, so I really have no idea what you are referring to.
This is not 10nm specific. It is applicable for other nms also. Its specific to the frequency being set. If vco_recalc returns the same value as being set by vco_set_rate, vco_set_rate will not be invoked second time onwards.
For example: Lets take below devices:
Cheza is based on SDM845 which is 10nm only. Clk frequency:206016 dsi_pll_10nm_vco_set_rate - DSI PLL0 rate=1236096000 dsi_pll_10nm_vco_recalc_rate - DSI PLL0 returning vco rate = 1236095947
Trogdor is based on sc7180 which is also 10nm. Clk frequency:69300 dsi_pll_10nm_vco_set_rate - DSI PLL0 rate=1663200000 dsi_pll_10nm_vco_recalc_rate - DSI PLL0 returning vco rate = 1663200000
In same trogdor device, we slightly changed the clock frequency and the values actually differ which will not cause any issue. Clk frequency:69310 dsi_pll_10nm_vco_set_rate - DSI PLL0 rate=1663440000 dsi_pll_10nm_vco_recalc_rate - DSI PLL0 returning vco rate = 1663439941
tbh, loosing state when power is off is kind of the behavior that I'd expect. It kinda makes me wonder if things are not getting powered off all the way on some SoCs?
jhugo, are you worried that this patch will cause problems on other users of the 10nm pll?
Essentially yes. Conceptually it doesn't seem like this change should cause any harm, however -
This sounds like we are trying to work around the clk framework, which seems wrong. It feels like we should be able to set a clk flag for this and make the framework deal with it.
Also, this fix is 10nm specific, yet this issue affects all implementations? Seems like this should perhaps be in common code so that we don't need to play whack-a-mole by fixing every implementation piecemeal.
Finally, the PLLs are notorious for not taking a configuration unless they are running. I admit, I haven't looked at this patch in detail to determine if that is the case here, but there doesn't seem to be any indication from the commit test or a comment that doing so is actually valid in all cases.