EDP_PSR2_FRAME_BEFORE_SU() is the number of frames that PSR2 HW will wait before enter in PSR2 activation state, important to note here is that it will wait for X frames not X idle frames. So lets reuse the previous approch to get the maximum number of frames between 6 and sink_sync_latency to enter in PSR2 activation state and just remove the VBT idle_frames.
And EDP_PSR2_FRAME_BEFORE_SU() is the number of idle frames that PSR2 HW will wait before enter in PSR2 deep sleep when PSR2 is active. Important note here is that HW will need to go to PSR2 idle state every time it exits PSR2 deep sleep, so avoid as much as possible deep sleep will provide in overal more power savings as PSR2 sleep will save some power as memory will not be read in the idle frames and screen will be partialy updated without exit PSR2.
Cc: Rodrigo Vivi rodrigo.vivi@intel.com Cc: Dhinakaran Pandiyan dhinakaran.pandiyan@intel.com Signed-off-by: José Roberto de Souza jose.souza@intel.com --- drivers/gpu/drm/i915/intel_psr.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 0257dbcf9384..36c2eb27ed8d 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -489,18 +489,20 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
/* Let's use 6 as the minimum to cover all known cases including the * off-by-one issue that HW has in some cases. + * sink_sync_latency of 8 means source has to wait for more than 8 + * frames, so sink_sync_latency + 1. */ - int idle_frames = max(6, dev_priv->vbt.psr.idle_frames); + val = max(6, dev_priv->psr.sink_sync_latency + 1); + val = min_t(u32, val, EDP_PSR2_FRAME_BEFORE_SU_MAX); + val = EDP_PSR2_FRAME_BEFORE_SU(val);
- idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); - val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT; + /* Avoid deep sleep as much as possible to avoid PSR2 idle state */ + val |= EDP_PSR2_IDLE_FRAME(EDP_PSR2_IDLE_FRAME_MAX);
val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) val |= EDP_Y_COORDINATE_ENABLE;
- val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); - if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 && dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50) val |= EDP_PSR2_TP2_TIME_50us;