On Fri, Sep 07, 2018 at 03:22:30PM +0800, Icenowy Zheng wrote:
By experiments it seems that the A64 HDMI PHY is not able to use the second video PLL as the clock parent.
Drop pll-1 from the device tree binding of A64 HDMI PHY.
Signed-off-by: Icenowy Zheng icenowy@aosc.io
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 - 1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index f8773ecb7525..62034039cee1 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -114,7 +114,6 @@ Required properties:
H3 and A64 HDMI PHY require additional clocks:
- pll-0: parent of phy clock
- pll-1: second possible phy clock parent (A64 only)
You shouldn't need to do this. The DT is about the hardware. The fact that we haven't figured out how to use it is quite irrelevant, and can change in the future, unlike this binding.
Maxime