Re: [PATCH v9 03/14] dt-bindings: mediatek: display: split each block to individual yaml

Hi, Jason:

jason-jh.lin jason-jh.lin@mediatek.com 於 2021年8月25日 週三 下午10:48寫道：

1. Remove mediatek,dislpay.txt
2. Split each display function block to individual yaml file.

Signed-off-by: jason-jh.lin jason-jh.lin@mediatek.com

[snip]

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml new file mode 100644 index 000000000000..faa764c12dfc --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#

+title: mediatek display adaptive ambient light processor

+maintainers:

• • Chun-Kuang Hu chunkuang.hu@kernel.org
• • Philipp Zabel p.zabel@pengutronix.de

+description: |

• The mediatek display adaptive ambient light processor, namely AAL,

Mediatek

• is responsible for backlight power saving and sunlight visibility improving.
• AAL device node must be siblings to the central MMSYS_CONFIG node.
• For a description of the MMSYS_CONFIG binding, see
• Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.

+properties:

• compatible:
• oneOf:

•  - items:
  

•      - const: mediatek,mt8173-disp-aal
  

•  - items:
  

•      - enum:
  

•          - mediatek,mt2712-disp-aal
  

•          - mediatek,mt8183-disp-aal
  

•      - enum:
  

•          - mediatek,mt8173-disp-aal
  

• reg:
• maxItems: 1
• interrupts:
• maxItems: 1
• power-domains:
• description: A phandle and PM domain specifier as defined by bindings of

•  the power controller specified by phandle. See
  

•  Documentation/devicetree/bindings/power/power-domain.yaml for details.
  

• clocks:
• items:

•  - description: AAL Clock
  

• mediatek,gce-client-reg:
• description:

•  The register of client driver can be configured by gce with 4 arguments defined
  

•  in this property, such as phandle of gce, subsys id, register offset and size.
  

•  Each subsys id is mapping to a base address of display function blocks register
  

•  which is defined in the gce header include/include/dt-bindings/gce/<chip>-gce.h.
  

include/dt-bindings/gce/<chip>-gce.h.

• $ref: /schemas/types.yaml#/definitions/phandle-array
• maxItems: 1

+required:

• • compatible
• • reg
• • interrupts
• • power-domains
• • clocks

+additionalProperties: false

+examples:

• • |
• aal@14015000 {

•    compatible = "mediatek,mt8173-disp-aal";
  

•    reg = <0 0x14015000 0 0x1000>;
  

•    interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
  

•    power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•    clocks = <&mmsys CLK_MM_DISP_AAL>;
  

•    mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
  

• };

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml new file mode 100644 index 000000000000..e848879d755c --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ccorr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#

+title: mediatek Ddsplay color correction

display

+maintainers:

• • Chun-Kuang Hu chunkuang.hu@kernel.org
• • Philipp Zabel p.zabel@pengutronix.de

+description: |

• The mediatek display color correction, namely CCORR, reproduces correct color
• on panels with different color gamut.
• CCORR device node must be siblings to the central MMSYS_CONFIG node.
• For a description of the MMSYS_CONFIG binding, see
• Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.

+properties:

• compatible:
• oneOf:

•  - items:
  

•      - const: mediatek,mt8183-disp-ccorr
  

• reg:
• maxItems: 1
• interrupts:
• maxItems: 1
• power-domains:
• description: A phandle and PM domain specifier as defined by bindings of

•  the power controller specified by phandle. See
  

•  Documentation/devicetree/bindings/power/power-domain.yaml for details.
  

• clocks:
• items:

•  - description: CCORR Clock
  

• mediatek,gce-client-reg:
• description:

•  The register of client driver can be configured by gce with 4 arguments defined
  

•  in this property, such as phandle of gce, subsys id, register offset and size.
  

•  Each subsys id is mapping to a base address of display function blocks register
  

•  which is defined in the gce header include/include/dt-bindings/gce/<chip>-gce.h.
  

• $ref: /schemas/types.yaml#/definitions/phandle-array
• maxItems: 1

+required:

• • compatible
• • reg
• • interrupts
• • power-domains
• • clocks

+additionalProperties: false

+examples:

• • |
• ccorr0: ccorr@1400f000 {

•    compatible = "mediatek,mt8183-disp-ccorr";
  

•    reg = <0 0x1400f000 0 0x1000>;
  

•    interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
  

•    power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
  

•    clocks = <&mmsys CLK_MM_DISP_CCORR0>;
  

•    mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
  

• };

[snip]

new file mode 100644 index 000000000000..d2e957cf1c61 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,od.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#

+title: mediatek display overdirve

+maintainers:

• • Chun-Kuang Hu chunkuang.hu@kernel.org
• • Philipp Zabel p.zabel@pengutronix.de

+description: |

• The mediatek display overdrive, namely OD, increases the transition values
• of pixels between consecutive frames to make LCD rotate faster.
• OD device node must be siblings to the central MMSYS_CONFIG node.
• For a description of the MMSYS_CONFIG binding, see
• Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.

+properties:

• compatible:
• oneOf:

•  - items:
  

•      - const: mediatek,mt2712-disp-od
  

•  - items:
  

•      - const: mediatek,mt8173-disp-od
  

• reg:
• maxItems: 1
• interrupts:
• maxItems: 1
• clocks:
• items:

•  - description: OVL Clock
  

OD Clock?

+required:

• • compatible
• • reg
• • clocks

+additionalProperties: false

+examples:

• • |
• od@14023000 {

•    compatible = "mediatek,mt8173-disp-od";
  

•    reg = <0 0x14023000 0 0x1000>;
  

•    clocks = <&mmsys CLK_MM_DISP_OD>;
  

• };

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml new file mode 100644 index 000000000000..60eb29c79b84 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl-2l.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#

+title: mediatek display overlay 2 layer

+maintainers:

• • Chun-Kuang Hu chunkuang.hu@kernel.org
• • Philipp Zabel p.zabel@pengutronix.de

+description: |

• The mediatek display overlay provides 2 more layer for OVL.
• OVL-2L device node must be siblings to the central MMSYS_CONFIG node.
• For a description of the MMSYS_CONFIG binding, see
• Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
• for details.

+properties:

• compatible:
• oneOf:

•  - items:
  

•      - const: mediatek,mt8183-disp-ovl-2l
  

• reg:
• maxItems: 1
• interrupts:
• maxItems: 1
• power-domains:
• description: A phandle and PM domain specifier as defined by bindings of

•  the power controller specified by phandle. See
  

•  Documentation/devicetree/bindings/power/power-domain.yaml for details.
  

• clocks:
• items:

•  - description: OVL-2L Clock
  

• iommus:
• description:

•  This property should point to the respective IOMMU block with master port as argument,
  

•  see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
  

• mediatek,larb:
• description:

•  This property should contain a phandle pointing to the local arbiter deviceas defined in
  

devices

•  Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
  

•  It must sort according to the local arbiter index, like larb0, larb1, larb2...
  

• $ref: /schemas/types.yaml#/definitions/phandle-array
• minItems: 1
• maxItems: 32
• mediatek,gce-client-reg:
• description:

•  The register of client driver can be configured by gce with 4 arguments defined
  

•  in this property, such as phandle of gce, subsys id, register offset and size.
  

•  Each subsys id is mapping to a base address of display function blocks register
  

•  which is defined in the gce header include/include/dt-bindings/gce/<chip>-gce.h.
  

• $ref: /schemas/types.yaml#/definitions/phandle-array
• maxItems: 1

+required:

• • compatible
• • reg
• • interrupts
• • power-domains
• • clocks
• • iommus

+additionalProperties: false

+examples:

• • |
• ovl_2l0: ovl@14009000 {

•    compatible = "mediatek,mt8183-disp-ovl-2l";
  

•    reg = <0 0x14009000 0 0x1000>;
  

•    interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
  

•    power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
  

•    clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
  

•    iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
  

•    mediatek,larb = <&larb0>;
  

•    mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
  

• };

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml new file mode 100644 index 000000000000..a0c29cd3377a --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#

+title: mediatek display overlay

+maintainers:

• • Chun-Kuang Hu chunkuang.hu@kernel.org
• • Philipp Zabel p.zabel@pengutronix.de

+description: |

• The mediatek display overlay, namely OVL, can do alpha blending from the memory.
• OVL device node must be siblings to the central MMSYS_CONFIG node.
• For a description of the MMSYS_CONFIG binding, see
• Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
• for details.

+properties:

• compatible:
• oneOf:

•  - items:
  

•      - const: mediatek,mt2701-disp-ovl
  

•  - items:
  

•      - const: mediatek,mt8173-disp-ovl
  

•  - items:
  

•      - const: mediatek,mt8183-disp-ovl
  

•  - items:
  

•      - enum:
  

•          - mediatek,mt7623-disp-ovl
  

•          - mediatek,mt2712-disp-ovl
  

•      - enum:
  

•          - mediatek,mt2701-disp-ovl
  

Why mediatek,mt8192-disp-ovl disapear?

• reg:
• maxItems: 1
• interrupts:
• maxItems: 1
• power-domains:
• description: A phandle and PM domain specifier as defined by bindings of

•  the power controller specified by phandle. See
  

•  Documentation/devicetree/bindings/power/power-domain.yaml for details.
  

• clocks:
• items:

•  - description: OVL Clock
  

• iommus:
• description:

•  This property should point to the respective IOMMU block with master port as argument,
  

•  see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
  

• mediatek,larb:
• description:

•  This property should contain a phandle pointing to the local arbiter deviceas defined in
  

•  Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
  

•  It must sort according to the local arbiter index, like larb0, larb1, larb2...
  

• $ref: /schemas/types.yaml#/definitions/phandle-array
• minItems: 1
• maxItems: 32
• mediatek,gce-client-reg:
• description:

•  The register of client driver can be configured by gce with 4 arguments defined
  

•  in this property, such as phandle of gce, subsys id, register offset and size.
  

•  Each subsys id is mapping to a base address of display function blocks register
  

•  which is defined in the gce header include/include/dt-bindings/gce/<chip>-gce.h.
  

• $ref: /schemas/types.yaml#/definitions/phandle-array
• maxItems: 1

+required:

• • compatible
• • reg
• • interrupts
• • power-domains
• • clocks
• • iommu

+additionalProperties: false

+examples:

• • |
• ovl0: ovl@1400c000 {

•    compatible = "mediatek,mt8173-disp-ovl";
  

•    reg = <0 0x1400c000 0 0x1000>;
  

•    interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
  

•    power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•    clocks = <&mmsys CLK_MM_DISP_OVL0>;
  

•    iommus = <&iommu M4U_PORT_DISP_OVL0>;
  

•    mediatek,larb = <&larb0>;
  

•    mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
  

• };