On 03/19/2015 02:18 AM, Hyungwon Hwang wrote:
Dear Daniel,
On Thu, 19 Mar 2015 01:13:21 +0000 Daniel Stone daniel-rLtY4a/8tF1rovVCs/uTlw@public.gmane.org wrote:
Hi Hyungwon,
On 19 March 2015 at 01:02, Hyungwon Hwang human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org wrote:
/** The input PLL clock for MIPI DSI in Exynos5433 seemsto be fixed
* by OSC CLK.*/fin = 24 * MHZ;Er, is this always true on other platforms as well? Shouldn't this be a part of the DeviceTree description?
I forgot to change the comment in development. Finally it is found that all exynos mipi dsi's fin is OSC clk which is 24 MHz. So I will remove the comment, but remain the code as it is.
Fair enough. Should pll_clk be removed from the DT description then, if it's fixed to the oscillator?
Yes. It is redundant to represent pll_clk in DT, and it should be removed.
Why do you think OSC clk determines value of pll_clk? pll_clk is mapped to SCLK_MIPI[01] or SCLK_DSIM0 gate with few dividers and muxes above. So at least in theory it can differ from osc clk. Additionally this gate should be enabled so you cannot just remove it from DT.
Regards Andrzej
Thanks for your review. I will send it again with the changes you suggested.
Thanks very much!
Cheers, Daniel
Best regards, Hyungwon Hwang -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html