Re: [PATCH 1/2] radeon: fix mipmap level 0 and 1 alignment for SI and CIK

On Fre, 2013-11-15 at 18:55 +0100, Marek Olšák wrote:

From: Michel Dänzer michel.daenzer@amd.com

Signed-off-by: Marek Olšák marek.olsak@amd.com

[...]

@@ -1657,10 +1659,7 @@ static int si_surface_init_2d(struct radeon_surface_manager *surf_man, tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT; break; case SI_TILE_MODE_DEPTH_STENCIL_2D:

•            if (surf_man->family >= CHIP_BONAIRE)
  

•                tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D;
  

•            else
  

•                tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
  

•            tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
             break;
         default:
             return -EINVAL;
  

This hunk should be in patch 2.

Other than that, the series is

Reviewed-and-Tested-by: Michel Dänzer michel.daenzer@amd.com

However, patch 2 also depends on the corresponding kernel support, which I just submitted.

Thanks for ironing out the kinks of this, Marek!