On Mon, Oct 22, 2012 at 9:44 AM, Alan Cox alan@lxorguk.ukuu.org.uk wrote:
That (walking all parent nodes) is probably the safest thing to do. I'm not sure whether it's optimal. It would likely depend on whether you can meaningfully have a bridge that's faster on the downstream side than on the upstream.
This is architecture goo at heart - would this be better as a helper in the PCI and arch PCI code ?
Good point.
POWER is not the only architecture where host bridges do not appear as devices in PCI config space -- ia64 has that, too. So the comment is too specific.
The link is a point-to-point thing, so this should be a local negotiation between the radeon device and the upstream bridge. I don't see the point of walking any farther up the chain.
drm_pcie_get_speed_cap_mask() should also be changed to use pcie_capability_read_dword() to avoid any issues with v1/v2 PCI Express Capability structures.
Bjorn