Extract the hardware initialisation part from malidp_se_irq_init() into the malidp_se_irq_hw_init() which will be later invoked from malidpxxx_enable_memwrite() when it needs to re-enable the interrupts.
Signed-off-by: Ayan Kumar Halder ayan.halder@arm.com Change-Id: Ibb26e86b38141993539307705695e3f6a9e32caa --- drivers/gpu/drm/arm/malidp_hw.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c index 3e73370..f5633bc 100644 --- a/drivers/gpu/drm/arm/malidp_hw.c +++ b/drivers/gpu/drm/arm/malidp_hw.c @@ -163,6 +163,7 @@ static const u16 dp500_se_scaling_coeffs[][SE_N_SCALING_COEFFS] = { };
#define MALIDP_DE_DEFAULT_PREFETCH_START 5 +static void malidp_se_irq_hw_init(struct malidp_hw_device *hwdev);
static int malidp500_query_hw(struct malidp_hw_device *hwdev) { @@ -952,6 +953,16 @@ static irqreturn_t malidp_se_irq(int irq, void *arg) return IRQ_HANDLED; }
+static void malidp_se_irq_hw_init(struct malidp_hw_device *hwdev) +{ + /* ensure interrupts are disabled */ + malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff); + malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff); + + malidp_hw_enable_irq(hwdev, MALIDP_SE_BLOCK, + hwdev->hw->map.se_irq_map.irq_mask); +} + static irqreturn_t malidp_se_irq_thread_handler(int irq, void *arg) { return IRQ_HANDLED; @@ -975,8 +986,7 @@ int malidp_se_irq_init(struct drm_device *drm, int irq) return ret; }
- malidp_hw_enable_irq(hwdev, MALIDP_SE_BLOCK, - hwdev->hw->map.se_irq_map.irq_mask); + malidp_se_irq_hw_init(hwdev);
return 0; }