+Daniel
On Tue, Mar 16, 2021 at 04:57:46PM -0700, Swathi Dhanavanthri wrote:
This is a permanent workaround for TGL,RKL,DG1 and ADLS.
Signed-off-by: Swathi Dhanavanthri swathi.dhanavanthri@intel.com
drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 +++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 3b4a7da60f0b..01f34a6bdf3e 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1117,11 +1117,38 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); }
+/*
- Though there are per-engine instances of these registers,
- they retain their value through engine resets and should
- only be provided on the GT workaround list rather than
- the engine-specific workaround list.
extra blank line here. Otherwise:
Reviewed-by: Lucas De Marchi lucas.demarchi@intel.com
Daniel, where/how should we land this and next pending WAs? I have 3 more already reviewed that I need to re-submit to dri-devel. Should we get an ack and merge intel-gt-next? Or maybe create a topic branch to be merged somewhere later?
thanks Lucas De Marchi
- */
+static void +wa_14011060649(struct drm_i915_private *i915, struct i915_wa_list *wal) +{
- struct intel_engine_cs *engine;
- struct intel_gt *gt = &i915->gt;
- int id;
- for_each_engine(engine, gt, id) {
if ((engine->class != VIDEO_DECODE_CLASS) ||(engine->instance % 2))continue;wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base),IECPUNIT_CLKGATE_DIS);- }
+}
static void gen12_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) { wa_init_mcr(i915, wal);
- /* Wa_14011060649:tgl,rkl,dg1,adls */
- wa_14011060649(i915, wal);
}
static void diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e5dd0203991b..cc60556306e2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2715,6 +2715,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */
+#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10) +#define IECPUNIT_CLKGATE_DIS REG_BIT(22)
#define ERROR_GEN6 _MMIO(0x40a0) #define GEN7_ERR_INT _MMIO(0x44040)
#define ERR_INT_POISON (1 << 31)
2.20.1
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