RE: [PATCH v2 1/2] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings

Hi Laurent,

Thanks for the feedback.

Subject: Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings

Hi Biju,

Thank you for the patch.

On Mon, Mar 28, 2022 at 07:49:30AM +0100, Biju Das wrote:

...

The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It can operate in DSI mode, with up to four data lanes.

Signed-off-by: Biju Das biju.das.jz@bp.renesas.com

v1->v2:

• Added full path for dsi-controller.yaml
• Modeled DSI + D-PHY as single block and updated reg property
• Fixed typo D_PHY->D-PHY
• Updated description
• Added interrupts and interrupt-names and updated the example

RFC->v1:

• Added a ref to dsi-controller.yaml.

RFC:-

---

.../bindings/display/bridge/renesas,dsi.yaml | 175 ++++++++++++++++++ 1 file changed, 175 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml new file mode 100644 index 000000000000..eebbf617c484 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yam +++ l @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 +--- +$id:

+title: Renesas RZ/G2L MIPI DSI Encoder

+maintainers:

• • Biju Das biju.das.jz@bp.renesas.com

+description: |

• This binding describes the MIPI DSI encoder embedded in the Renesas
• RZ/G2L alike family of SoC's. The encoder can operate in DSI mode,

+with

• up to four data lanes.

+allOf:

• • $ref: /schemas/display/dsi-controller.yaml#

+properties:

• compatible:
• enum:

•  - renesas,rzg2l-mipi-dsi # RZ/G2L and RZ/V2L
  

• reg:
• maxItems: 1
• interrupts:
• items:

•  - description: Sequence operation channel 0 interrupt
  

•  - description: Sequence operation channel 1 interrupt
  

•  - description: Video-Input operation channel 1 interrupt
  

•  - description: DSI Packet Receive interrupt
  

•  - description: DSI Fatal Error interrupt
  

•  - description: DSI D-PHY PPI interrupt
  

•  - description: Debug interrupt
  

• interrupt-names:
• items:

•  - const: seq0
  

•  - const: seq1
  

•  - const: vin1
  

•  - const: rcv
  

•  - const: ferr
  

•  - const: ppi
  

•  - const: debug
  

• clocks:
• items:

•  - description: DSI D-PHY PLL multiplied clock
  

•  - description: DSI D-PHY system clock
  

•  - description: DSI AXI bus clock
  

•  - description: DSI Register access clock
  

•  - description: DSI Video clock
  

•  - description: DSI D-PHY Escape mode Receive clock
  

Isn't this the escape mode *transmit* clock ?

Yep, There is a mismatch between clk document and hardware manual. I have reported this issue to HW team for fixing the clk document.

...

• clock-names:
• items:

•  - const: pllclk
  

•  - const: sysclk
  

•  - const: aclk
  

•  - const: pclk
  

•  - const: vclk
  

•  - const: lpclk
  

• resets:
• items:

•  - description: MIPI_DSI_CMN_RSTB
  

•  - description: MIPI_DSI_ARESET_N
  

•  - description: MIPI_DSI_PRESET_N
  

• reset-names:
• items:

•  - const: rst
  

•  - const: arst
  

•  - const: prst
  

• power-domains:
• maxItems: 1
• ports:
• $ref: /schemas/graph.yaml#/properties/ports
• properties:

•  port@0:
  

•    $ref: /schemas/graph.yaml#/properties/port
  

•    description: Parallel input port
  

•  port@1:
  

•    $ref: /schemas/graph.yaml#/$defs/port-base
  

•    unevaluatedProperties: false
  

•    description: DSI output port
  

•    properties:
  

•      endpoint:
  

•        $ref: /schemas/media/video-interfaces.yaml#
  

•        unevaluatedProperties: false
  

•        properties:
  

•          data-lanes:
  

•            minItems: 1
  

•            maxItems: 4
  

You should specify the acceptable values, especially given that the hardware doesn't seem to support lane reordering.

OK.

...

•        required:
  

•          - data-lanes
  

• required:

•  - port@0
  

•  - port@1
  

+required:

• • compatible
• • reg
• • interrupts
• • interrupt-names
• • clocks
• • clock-names
• • resets
• • reset-names
• • power-domains
• • ports

+additionalProperties: false

+examples:

• • |
• #include <dt-bindings/interrupt-controller/arm-gic.h>
• #include <dt-bindings/clock/r9a07g044-cpg.h>

Could you please swap those two lines to get them sorted alphabetically ?

OK.

Cheers, Biju

With these comments addressed,

Reviewed-by: Laurent Pinchart laurent.pinchart@ideasonboard.com

...

• dsi0: dsi@10850000 {

•    compatible = "renesas,rzg2l-mipi-dsi";
  

•    reg = <0x10850000 0x20000>;
  

•    interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
  

•                 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
  

•                 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
  

•                 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
  

•                 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
  

•                 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
  

•                 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
  

•    interrupt-names = "seq0", "seq1", "vin1", "rcv",
  

•                      "ferr", "ppi", "debug";
  

•    clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
  

•             <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
  

•             <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
  

•             <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
  

•             <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
  

•             <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
  

•    clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk",
  

"lpclk";

...

•    resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
  

•             <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
  

•             <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
  

•    reset-names = "rst", "arst", "prst";
  

•    power-domains = <&cpg>;
  

•    ports {
  

•        #address-cells = <1>;
  

•        #size-cells = <0>;
  

•        port@0 {
  

•            reg = <0>;
  

•            dsi0_in: endpoint {
  

•                remote-endpoint = <&du_out_dsi0>;
  

•            };
  

•        };
  

•        port@1 {
  

•            reg = <1>;
  

•            dsi0_out: endpoint {
  

•                data-lanes = <1 2 3 4>;
  

•                remote-endpoint = <&adv7535_in>;
  

•            };
  

•        };
  

•    };
  

• };

+...

-- Regards,

Laurent Pinchart