4 Jan
2020
4 Jan
'20
9:29 p.m.
On Tue, 24 Dec 2019 15:38:51 +0100, Miquel Raynal wrote:
PX30 SoCs use a single PHY shared by two display pipelines: MIPI DSI and LVDS. In the case of the LVDS IP, document the possibility to fill a PHY handle.
Signed-off-by: Miquel Raynal miquel.raynal@bootlin.com
.../devicetree/bindings/display/rockchip/rockchip-lvds.txt | 3 +++ 1 file changed, 3 insertions(+)
Acked-by: Rob Herring robh@kernel.org