Except typo, the changes look good to me. Reviewed-by: Gwan-gyeong Mun gwan-gyeong.mun@intel.com On Wed, 2019-09-18 at 19:03 +0000, Mun, Gwan-gyeong wrote:
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
From: Ville Syrjälä ville.syrjala@linux.intel.com
On HSW the pipe colorspace is configured via PIPECONF (as opposed to PIPEMISC in BDW+). Let's configure+readout that stuff correctly.
Enablling YCbCr 4:4:4 output will now be a simple matter of
Typo: Enablling -> Enabling
setting crtc_state->output_format appropriately in the encoder .compute_config().
Signed-off-by: Ville Syrjälä ville.syrjala@linux.intel.com
drivers/gpu/drm/i915/display/intel_display.c | 13 ++++++++++++- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 1dd1aa29a649..bd3ff96c1618 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -9430,6 +9430,10 @@ static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state) else val |= PIPECONF_PROGRESSIVE;
- if (IS_HASWELL(dev_priv) &&
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;- I915_WRITE(PIPECONF(cpu_transcoder), val); POSTING_READ(PIPECONF(cpu_transcoder));
} @@ -10423,7 +10427,14 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
intel_get_pipe_src_size(crtc, pipe_config);
- if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
- if (IS_HASWELL(dev_priv)) {
u32 tmp = I915_READ(PIPECONF(pipe_config-cpu_transcoder));
if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)pipe_config->output_format =INTEL_OUTPUT_FORMAT_YCBCR444;
elsepipe_config->output_format =INTEL_OUTPUT_FORMAT_RGB;
- } else { pipe_config->output_format = bdw_get_pipemisc_output_format(crtc);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 66f7f417231f..58471312b8b2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5712,6 +5712,7 @@ enum { #define PIPECONF_CXSR_DOWNCLOCK (1 << 16) #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14) #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) +#define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW (1 << 11) /* hsw only */ #define PIPECONF_BPC_MASK (0x7 << 5) #define PIPECONF_8BPC (0 << 5) #define PIPECONF_10BPC (1 << 5)
Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx