This patch series reworks DPU's irq handling code by merging dpu_core_irq into dpu_hw_intr, reworking/dropping irq-related helpers and wrappers, etc.
Changes since v1: - Rework callbacks registration code to allow just single callback per interrupt. This removes need to do any memory allocation in reg/unreg code and simplifies handling of interrupts.
The following changes since commit 7e0230fd096c03e9662e66150f951075dd16e496:
drm/msm/mdp5: provide dynamic bandwidth management (2021-06-17 09:51:44 -0700)
are available in the Git repository at:
https://git.linaro.org/people/dmitry.baryshkov/kernel.git dpu-irq-simplify-5
for you to fetch changes up to b2ae835c61b2065037c55b4596e16053484f4904:
drm/msm/dpu: remove struct dpu_encoder_irq and enum dpu_intr_idx (2021-06-18 01:12:04 +0300)
---------------------------------------------------------------- Dmitry Baryshkov (7): drm/msm/dpu: squash dpu_core_irq into dpu_hw_interrupts drm/msm/dpu: don't clear IRQ register twice drm/msm/dpu: merge struct dpu_irq into struct dpu_hw_intr drm/msm/dpu: allow just single IRQ callback drm/msm/dpu: remove extra wrappers around dpu_core_irq drm/msm/dpu: get rid of dpu_encoder_helper_(un)register_irq drm/msm/dpu: remove struct dpu_encoder_irq and enum dpu_intr_idx
drivers/gpu/drm/msm/Makefile | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 256 -------------------- drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 30 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 111 ++------- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 66 +----- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 99 ++++---- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 56 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 264 +++++++++++++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 96 +------- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 27 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 25 -- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 51 ++-- 12 files changed, 334 insertions(+), 748 deletions(-) delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c