On BCM2711 to avoid stale pixels getting stuck in intermediate FIFOs, the pixelvalve needs to be setup each time there's a mode change or enable / disable sequence.
Therefore, we can't really use mode_set_nofb anymore to configure it, but we need to move it to atomic_enable.
Signed-off-by: Maxime Ripard maxime@cerno.tech --- drivers/gpu/drm/vc4/vc4_crtc.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index a69e0d456b79..08bd595f6a7c 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -374,14 +374,6 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc) } }
-static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) -{ - struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); - - if (!vc4_state->feed_txp) - vc4_crtc_config_pv(crtc); -} - static void require_hvs_enabled(struct drm_device *dev) { struct vc4_dev *vc4 = to_vc4_dev(dev); @@ -443,6 +435,9 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
vc4_crtc_pixelvalve_reset(crtc);
+ if (!vc4_state->feed_txp) + vc4_crtc_config_pv(crtc); + CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);
/* Enable vblank irq handling before crtc is started otherwise @@ -814,7 +809,6 @@ static const struct drm_crtc_funcs vc4_crtc_funcs = { };
static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = { - .mode_set_nofb = vc4_crtc_mode_set_nofb, .mode_valid = vc4_crtc_mode_valid, .atomic_check = vc4_crtc_atomic_check, .atomic_flush = vc4_hvs_atomic_flush,